#ifndef __SN8F27E23__H
#define __SN8F27E23__H

void _ClearWatchDogTimer(void);
void _ClrRAM(void);

#define NOP(X)  	__asm{	_NOP X }
#define LOG(X)  	__asm{	LOG CNameToAsmLabel(X) }
sfr	L = 0x80;
sfr	H = 0x81;
sfr	R = 0x82;
sfr	Z = 0x83;
sfr	Y = 0x84;
sfr	X = 0x85;
sfr	PFLAG = 0x86;
sbit	FZ = 0x86:0;
sbit	FDC = 0x86:1;
sbit	FC = 0x86:2;
sbit	FSTKOV = 0x86:4;
sbit	FRST = 0x86:5;
sbit	FWDT = 0x86:6;
sbit	FPOR = 0x86:7;
sfr	W0 = 0x88;
sfr	W1 = 0x89;
sfr	W2 = 0x8a;
sfr	W3 = 0x8b;
sfr	W4 = 0x8c;
sfr	W5 = 0x8d;
sfr	W6 = 0x8e;
sfr	W7 = 0x8f;
sfr	_HL = 0x90;
sfr	_YZ = 0x91;
sfr	PCL = 0x93;
sfr	PCH = 0x94;
sfr	OSCM = 0x95;
sbit	FCPUM1 = 0x95:4;
sbit	FCPUM0 = 0x95:3;
sbit	FCLKMD = 0x95:2;
sbit	FSTPHX = 0x95:1;
sfr	WDTR = 0x96;
sfr	INTRQ0 = 0x97;
sbit	FP40IRQ = 0x97:0;
sbit	FP41IRQ = 0x97:1;
sbit	FP42IRQ = 0x97:2;
sbit	FT0IRQ = 0x97:3;
sbit	FTC0IRQ = 0x97:4;
sbit	FTC1IRQ = 0x97:5;
sbit	FTC2IRQ = 0x97:6;
sbit	FTC3IRQ = 0x97:7;
sfr	INTRQ1 = 0x98;
sbit	FADCIRQ = 0x98:4;
sbit	FUTXIRQ = 0x98:3;
sbit	FURXIRQ = 0x98:2;
sbit	FSIOIRQ = 0x98:1;
sbit	FWAKEIRQ = 0x98:0;
sfr	P1W = 0x99;
sbit	FP17W = 0x99:7;
sbit	FP16W = 0x99:6;
sbit	FP15W = 0x99:5;
sbit	FP14W = 0x99:4;
sbit	FP13W = 0x99:3;
sbit	FP12W = 0x99:2;
sbit	FP11W = 0x99:1;
sbit	FP10W = 0x99:0;
sfr	INTEN0 = 0x9a;
sbit	FP40IEN = 0x9a:0;
sbit	FP41IEN = 0x9a:1;
sbit	FP42IEN = 0x9a:2;
sbit	FT0IEN = 0x9a:3;
sbit	FTC0IEN = 0x9a:4;
sbit	FTC1IEN = 0x9a:5;
sbit	FTC2IEN = 0x9a:6;
sbit	FTC3IEN = 0x9a:7;
sfr	INTEN1 = 0x9b;
sbit	FADCIEN = 0x9b:4;
sbit	FUTXIEN = 0x9b:3;
sbit	FURXIEN = 0x9b:2;
sbit	FSIOIEN = 0x9b:1;
sbit	FWAKEIEN = 0x9b:0;
sfr	PEDGE = 0x9f;
sbit	FP40G0 = 0x9f:0;
sbit	FP40G1 = 0x9f:1;
sbit	FP41G0 = 0x9f:2;
sbit	FP41G1 = 0x9f:3;
sbit	FP42G0 = 0x9f:4;
sbit	FP42G1 = 0x9f:5;
sfr	P1M = 0xa1;
sbit	FP10M = 0xa1:0;
sbit	FP11M = 0xa1:1;
sbit	FP12M = 0xa1:2;
sbit	FP13M = 0xa1:3;
sbit	FP14M = 0xa1:4;
sbit	FP15M = 0xa1:5;
sbit	FP16M = 0xa1:6;
sbit	FP17M = 0xa1:7;
sfr	P2M = 0xa2;
sbit	FP20M = 0xa2:0;
sbit	FP21M = 0xa2:1;
sfr	P4M = 0xa4;
sbit	FP40M = 0xa4:0;
sbit	FP41M = 0xa4:1;
sbit	FP42M = 0xa4:2;
sbit	FP43M = 0xa4:3;
sbit	FP44M = 0xa4:4;
sbit	FP45M = 0xa4:5;
sbit	FP46M = 0xa4:6;
sbit	FP47M = 0xa4:7;
sfr	P1 = 0xa7;
sbit	FP10 = 0xa7:0;
sbit	FP11 = 0xa7:1;
sbit	FP12 = 0xa7:2;
sbit	FP13 = 0xa7:3;
sbit	FP14 = 0xa7:4;
sbit	FP15 = 0xa7:5;
sbit	FP16 = 0xa7:6;
sbit	FP17 = 0xa7:7;
sfr	P2 = 0xa8;
sbit	FP20 = 0xa8:0;
sbit	FP21 = 0xa8:1;
sfr	P4 = 0xaa;
sbit	FP40 = 0xaa:0;
sbit	FP41 = 0xaa:1;
sbit	FP42 = 0xaa:2;
sbit	FP43 = 0xaa:3;
sbit	FP44 = 0xaa:4;
sbit	FP45 = 0xaa:5;
sbit	FP46 = 0xaa:6;
sbit	FP47 = 0xaa:7;
sfr	P1UR = 0xad;
sbit	FP10R = 0xad:0;
sbit	FP11R = 0xad:1;
sbit	FP12R = 0xad:2;
sbit	FP13R = 0xad:3;
sbit	FP14R = 0xad:4;
sbit	FP15R = 0xad:5;
sbit	FP16R = 0xad:6;
sbit	FP17R = 0xad:7;
sfr	P2UR = 0xae;
sbit	FP20R = 0xae:0;
sbit	FP21R = 0xae:1;
sfr	P4UR = 0xb0;
sbit	FP40R = 0xb0:0;
sbit	FP41R = 0xb0:1;
sbit	FP42R = 0xb0:2;
sbit	FP43R = 0xb0:3;
sbit	FP44R = 0xb0:4;
sbit	FP45R = 0xb0:5;
sbit	FP46R = 0xb0:6;
sbit	FP47R = 0xb0:7;
sfr	T0M = 0xb2;
sbit	FT0ENB = 0xb2:7;
sbit	FT0RATE2 = 0xb2:6;
sbit	FT0RATE1 = 0xb2:5;
sbit	FT0RATE0 = 0xb2:4;
sbit	FT0TB = 0xb2:0;
sfr	T0C = 0xb3;
sfr	TC0M = 0xb4;
sbit	FPWM0OUT = 0xb4:0;
sbit	FTC0PO = 0xb4:1;
sbit	FTC0CKS0 = 0xb4:2;
sbit	FTC0CKS1 = 0xb4:3;
sbit	FTC0RATE0 = 0xb4:4;
sbit	FTC0RATE1 = 0xb4:5;
sbit	FTC0RATE2 = 0xb4:6;
sbit	FTC0ENB = 0xb4:7;
sfr	TC0C = 0xb5;
sfr	TC0R = 0xb6;
sfr	TC0D = 0xb7;
sfr	TC1M = 0xb8;
sbit	FPWM1OUT = 0xb8:0;
sbit	FTC1PO = 0xb8:1;
sbit	FTC1CKS0 = 0xb8:2;
sbit	FTC1RATE0 = 0xb8:4;
sbit	FTC1RATE1 = 0xb8:5;
sbit	FTC1RATE2 = 0xb8:6;
sbit	FTC1ENB = 0xb8:7;
sfr	TC1C = 0xb9;
sfr	TC1R = 0xba;
sfr	TC1D = 0xbb;
sfr	TC2M = 0xbc;
sbit	FPWM2OUT = 0xbc:0;
sbit	FTC2PO = 0xbc:1;
sbit	FTC2CKS0 = 0xbc:2;
sbit	FTC2RATE0 = 0xbc:4;
sbit	FTC2RATE1 = 0xbc:5;
sbit	FTC2RATE2 = 0xbc:6;
sbit	FTC2ENB = 0xbc:7;
sfr	TC2C = 0xbd;
sfr	TC2R = 0xbe;
sfr	TC2D = 0xbf;
sfr	P4CON = 0xc6;
sfr	P1CON = 0xc7;
sbit	FP2CON0 = 0xc7:0;
sbit	FP2CON1 = 0xc7:1;
sbit	FP1CON6 = 0xc7:6;
sbit	FP1CON7 = 0xc7:7;
sfr	ADM = 0xc8;
sbit	FCHS0 = 0xc8:0;
sbit	FCHS1 = 0xc8:1;
sbit	FCHS2 = 0xc8:2;
sbit	FCHS3 = 0xc8:3;
sbit	FGCHS = 0xc8:4;
sbit	FEOC = 0xc8:5;
sbit	FADS = 0xc8:6;
sbit	FADENB = 0xc8:7;
sfr	ADB = 0xc9;
sfr	ADR = 0xca;
sbit	FADB0 = 0xca:0;
sbit	FADB1 = 0xca:1;
sbit	FADB2 = 0xca:2;
sbit	FADB3 = 0xca:3;
sbit	FADCKS0 = 0xca:4;
sbit	FADLEN = 0xca:5;
sbit	FADCKS1 = 0xca:6;
sbit	FTCHEN = 0xca:7;
sfr	ADT = 0xcb;
sbit	FADT0 = 0xcb:0;
sbit	FADT1 = 0xcb:1;
sbit	FADT2 = 0xcb:2;
sbit	FADT3 = 0xcb:3;
sbit	FADT4 = 0xcb:4;
sbit	FADTS0 = 0xcb:6;
sbit	FADTS1 = 0xcb:7;
sfr	VREFH = 0xcc;
sbit	FVHS0 = 0xcc:0;
sbit	FVHS1 = 0xcc:1;
sbit	FVHS2 = 0xcc:2;
sbit	FEVHENB = 0xcc:7;
sfr	TC3M = 0xd0;
sbit	FPWM3OUT = 0xd0:0;
sbit	FTC3PO = 0xd0:1;
sbit	FTC3CKS0 = 0xd0:2;
sbit	FTC3RATE0 = 0xd0:4;
sbit	FTC3RATE1 = 0xd0:5;
sbit	FTC3RATE2 = 0xd0:6;
sbit	FTC3ENB = 0xd0:7;
sfr	TC3C = 0xd1;
sfr	TC3R = 0xd2;
sfr	TC3D = 0xd3;
sfr	PWCH = 0xd4;
sbit	FPWCH10 = 0xd4:0;
sbit	FPWCH11 = 0xd4:1;
sbit	FPWCH20 = 0xd4:2;
sbit	FPWCH21 = 0xd4:3;
sbit	FPWCH30 = 0xd4:4;
sbit	FPWCH31 = 0xd4:5;
sfr	PWES = 0xd5;
sbit	FPW1ES0 = 0xd5:0;
sbit	FPW1ES1 = 0xd5:1;
sbit	FPW2ES0 = 0xd5:2;
sbit	FPW2ES1 = 0xd5:3;
sbit	FPW3ES0 = 0xd5:4;
sbit	FPW3ES1 = 0xd5:5;
sfr	P1DR = 0xd7;
sbit	FP13DR = 0xd7:0;
sbit	FP14DR = 0xd7:1;
sbit	FP15DR = 0xd7:2;
sbit	FP16DR = 0xd7:3;
sbit	FP13SC = 0xd7:4;
sbit	FP14SC = 0xd7:5;
sbit	FP15SC = 0xd7:6;
sbit	FP16SC = 0xd7:7;
sfr	PECMD = 0xdb;
sfr	PEROML = 0xdc;
sfr	PEROMH = 0xdd;
sfr	PERAML = 0xde;
sfr	PERAMCNT = 0xdf;
sfr	SIOM = 0xe0;
sbit	FSENB = 0xe0:7;
sbit	FSTART = 0xe0:6;
sbit	FSRATE1 = 0xe0:5;
sbit	FSRATE0 = 0xe0:4;
sbit	FMLSB = 0xe0:3;
sbit	FSCKMD = 0xe0:2;
sbit	FCPOL = 0xe0:1;
sbit	FCPHA = 0xe0:0;
sfr	SIOR = 0xe1;
sfr	SIOB = 0xe2;
sfr	URTX = 0xe4;
sbit	FUTXEN = 0xe4:7;
sbit	FUTXPEN = 0xe4:6;
sbit	FUTXPS = 0xe4:5;
sbit	FUTXBRK = 0xe4:4;
sbit	FURXBZ = 0xe4:3;
sbit	FUTXBZ = 0xe4:2;
sbit	FURMX = 0xe4:1;
sbit	FSIOMX = 0xe4:0;
sfr	URRX = 0xe5;
sbit	FURXEN = 0xe5:7;
sbit	FURXPEN = 0xe5:6;
sbit	FURXPS = 0xe5:5;
sbit	FURXPC = 0xe5:4;
sbit	FUFMER = 0xe5:3;
sbit	FURS2 = 0xe5:2;
sbit	FURS1 = 0xe5:1;
sbit	FURS0 = 0xe5:0;
sfr	URCR = 0xe6;
sfr	UTXD = 0xe7;
sfr	URXD = 0xe8;
sfr	STKP = 0xef;
sbit	FGIE = 0xef:7;
sbit	FLVD24 = 0xef:6;
sbit	FLVD33 = 0xef:5;
sbit	FSTKPB2 = 0xef:2;
sbit	FSTKPB1 = 0xef:1;
sbit	FSTKPB0 = 0xef:0;
sfr	STK7L = 0xF0;
sfr	STK7H = 0xF1;
sfr	STK6L = 0xF2;
sfr	STK6H = 0xF3;
sfr	STK5L = 0xF4;
sfr	STK5H = 0xF5;
sfr	STK4L = 0xF6;
sfr	STK4H = 0xF7;
sfr	STK3L = 0xF8;
sfr	STK3H = 0xF9;
sfr	STK2L = 0xFA;
sfr	STK2H = 0xFB;
sfr	STK1L = 0xFC;
sfr	STK1H = 0xFD;
sfr	STK0L = 0xFE;
sfr	STK0H = 0xFF;
#define SLEEPMODE __asm{SleepMode}
#define GREENMODE __asm{GreenMode}
#define SLOWMODE __asm{SLowMode}
#define SLOW2NORMAL __asm{Slow2Normal}
#endif
