#ifndef __SN8P2732__H
#define __SN8P2732__H

void _ClearWatchDogTimer(void);
void _ClrRAM(void);

#define NOP(X)  	__asm{	_NOP X }
#define LOG(X)  	__asm{	LOG CNameToAsmLabel(X) }
sfr	L = 0x80;
sfr	H = 0x81;
sfr	R = 0x82;
sfr	Z = 0x83;
sfr	Y = 0x84;
sfr	PFLAG = 0x86;
sbit	FZ = 0x86:0;
sbit	FDC = 0x86:1;
sbit	FC = 0x86:2;
sbit	FLVD24 = 0x86:4;
sbit	FLVD36 = 0x86:5;
sbit	FNPD = 0x86:6;
sbit	FNT0 = 0x86:7;
sfr	RBANK = 0x87;
sbit	FRBNKS0 = 0x87:0;
sfr	PW1NM = 0x90;
sbit	FPW1NEN = 0x90:7;
sbit	FPW1D2 = 0x90:6;
sbit	FPW1D1 = 0x90:5;
sbit	FPW1D0 = 0x90:4;
sbit	FPW1DEN = 0x90:3;
sbit	FPW1NV = 0x90:2;
sfr	PW1M = 0x93;
sbit	FPW1EN = 0x93:7;
sbit	FPW1RATE2 = 0x93:6;
sbit	FPW1RATE1 = 0x93:5;
sbit	FPW1RATE0 = 0x93:4;
sbit	FPW1CKS = 0x93:3;
sbit	FPW1LN1 = 0x93:2;
sbit	FPW1LN0 = 0x93:1;
sbit	FPW1S = 0x93:0;
sfr	PW2M = 0x94;
sbit	FPW2EN = 0x94:7;
sbit	FPW2RATE2 = 0x94:6;
sbit	FPW2RATE1 = 0x94:5;
sbit	FPW2RATE0 = 0x94:4;
sbit	FPW2CKS = 0x94:3;
sbit	FPW2LN1 = 0x94:2;
sbit	FPW2LN0 = 0x94:1;
sfr	PW2CHS = 0x95;
sbit	FPW2CH6 = 0x95:5;
sbit	FPW2CH5 = 0x95:4;
sbit	FPW2CH4 = 0x95:3;
sbit	FPW2CH3 = 0x95:2;
sbit	FPW2CH2 = 0x95:1;
sbit	FPW2CH1 = 0x95:0;
sfr	PW1RH = 0x96;
sbit	FPW1GS = 0x96:7;
sbit	FPW1GEN = 0x96:6;
sbit	FPW1GD = 0x96:5;
sbit	FPW1R11 = 0x96:3;
sbit	FPW1R10 = 0x96:2;
sbit	FPW1R9 = 0x96:1;
sbit	FPW1R8 = 0x96:0;
sfr	PW1RL = 0x97;
sfr	PW2RH = 0x98;
sbit	FPW2R11 = 0x98:3;
sbit	FPW2R10 = 0x98:2;
sbit	FPW2R9 = 0x98:1;
sbit	FPW2R8 = 0x98:0;
sfr	PW2RL = 0x99;
sfr	CMP0M = 0x9c;
sbit	FCM0EN = 0x9c:7;
sbit	FCM0IEN = 0x9c:6;
sbit	FCM0IRQ = 0x9c:5;
sbit	FCM0OEN = 0x9c:4;
sbit	FCM0REF = 0x9c:3;
sbit	FCM0OUT = 0x9c:2;
sbit	FCM0G1 = 0x9c:1;
sbit	FCM0G0 = 0x9c:0;
sfr	CMP1M = 0x9d;
sbit	FCM1EN = 0x9d:7;
sbit	FCM1IEN = 0x9d:6;
sbit	FCM1IRQ = 0x9d:5;
sbit	FCM1OEN = 0x9d:4;
sbit	FCM1REF = 0x9d:3;
sbit	FCM1OUT = 0x9d:2;
sbit	FCM1G1 = 0x9d:1;
sbit	FCM1G0 = 0x9d:0;
sfr	CMP2M = 0x9e;
sbit	FCM2EN = 0x9e:7;
sbit	FCM2IEN = 0x9e:6;
sbit	FCM2IRQ = 0x9e:5;
sbit	FCM2OEN = 0x9e:4;
sbit	FCM2REF = 0x9e:3;
sbit	FCM2OUT = 0x9e:2;
sbit	FCM2G1 = 0x9e:1;
sbit	FCM2G0 = 0x9e:0;
sfr	OPM = 0x9f;
sbit	FOP2EN = 0x9f:2;
sbit	FOP1EN = 0x9f:1;
sbit	FOP0EN = 0x9f:0;
sfr	T1M = 0xa0;
sbit	FT1ENB = 0xa0:7;
sbit	FT1RATE2 = 0xa0:6;
sbit	FT1RATE1 = 0xa0:5;
sbit	FT1RATE0 = 0xa0:4;
sbit	FCPTCKS = 0xa0:3;
sbit	FCPTStart = 0xa0:2;
sbit	FCPTG1 = 0xa0:1;
sbit	FCPTG0 = 0xa0:0;
sfr	T1CL = 0xa1;
sfr	T1CH = 0xa2;
sfr	P4CON = 0xae;
sfr	ADM = 0xB1;
sbit	FADENB = 0xB1:7;
sbit	FADS = 0xB1:6;
sbit	FEOC = 0xB1:5;
sbit	FGCHS = 0xB1:4;
sbit	FAVREFH = 0xB1:3;
sbit	FCHS2 = 0xB1:2;
sbit	FCHS1 = 0xB1:1;
sbit	FCHS0 = 0xB1:0;
sfr	ADB = 0xb2;
sfr	ADR = 0xb3;
sbit	FADCKS1 = 0xb3:6;
sbit	FADLEN = 0xb3:5;
sbit	FADCKS0 = 0xb3:4;
sbit	FADB3 = 0xb3:3;
sbit	FADB2 = 0xb3:2;
sbit	FADB1 = 0xb3:1;
sbit	FADB0 = 0xb3:0;
sfr	ADT = 0xb4;
sbit	FADTS1 = 0xb4:7;
sbit	FADTS0 = 0xb4:6;
sbit	FADT4 = 0xb4:4;
sbit	FADT3 = 0xb4:3;
sbit	FADT2 = 0xb4:2;
sbit	FADT1 = 0xb4:1;
sbit	FADT0 = 0xb4:0;
sfr	P0M = 0xb8;
sbit	FP05M = 0xb8:5;
sbit	FP04M = 0xb8:4;
sbit	FP02M = 0xb8:2;
sbit	FP01M = 0xb8:1;
sbit	FP00M = 0xb8:0;
sfr	PEDGE = 0xbf;
sbit	FP02G1 = 0xbf:5;
sbit	FP02G0 = 0xbf:4;
sbit	FP01G1 = 0xbf:3;
sbit	FP01G0 = 0xbf:2;
sbit	FP00G1 = 0xbf:1;
sbit	FP00G0 = 0xbf:0;
sfr	P1W = 0xc0;
sfr	P1M = 0xc1;
sbit	FP17M = 0xc1:7;
sbit	FP16M = 0xc1:6;
sbit	FP15M = 0xc1:5;
sbit	FP14M = 0xc1:4;
sbit	FP13M = 0xc1:3;
sbit	FP12M = 0xc1:2;
sbit	FP11M = 0xc1:1;
sbit	FP10M = 0xc1:0;
sfr	P4M = 0xc4;
sbit	FP47M = 0xc4:7;
sbit	FP46M = 0xc4:6;
sbit	FP45M = 0xc4:5;
sbit	FP44M = 0xc4:4;
sbit	FP43M = 0xc4:3;
sbit	FP42M = 0xc4:2;
sbit	FP41M = 0xc4:1;
sbit	FP40M = 0xc4:0;
sfr	P5M = 0xc5;
sbit	FP57M = 0xc5:7;
sbit	FP56M = 0xc5:6;
sbit	FP55M = 0xc5:5;
sbit	FP54M = 0xc5:4;
sbit	FP53M = 0xc5:3;
sbit	FP52M = 0xc5:2;
sbit	FP51M = 0xc5:1;
sbit	FP50M = 0xc5:0;
sfr	INTRQ = 0xc8;
sbit	FADCIRQ = 0xc8:7;
sbit	FT1IRQ = 0xc8:6;
sbit	FTC0IRQ = 0xc8:5;
sbit	FT0IRQ = 0xc8:4;
sbit	FP02IRQ = 0xc8:2;
sbit	FP01IRQ = 0xc8:1;
sbit	FP00IRQ = 0xc8:0;
sfr	INTEN = 0xc9;
sbit	FADCIEN = 0xc9:7;
sbit	FT1IEN = 0xc9:6;
sbit	FTC0IEN = 0xc9:5;
sbit	FT0IEN = 0xc9:4;
sbit	FP02IEN = 0xc9:2;
sbit	FP01IEN = 0xc9:1;
sbit	FP00IEN = 0xc9:0;
sfr	OSCM = 0xca;
sbit	FCPUM1 = 0xca:4;
sbit	FCPUM0 = 0xca:3;
sbit	FCLKMD = 0xca:2;
sbit	FSTPHX = 0xca:1;
sfr	WDTR = 0xcc;
sfr	TC0R = 0xcd;
sfr	PCL = 0xce;
sfr	PCH = 0xcf;
sfr	P0 = 0xd0;
sbit	FP05 = 0xd0:5;
sbit	FP04 = 0xd0:4;
sbit	FP03 = 0xd0:3;
sbit	FP02 = 0xd0:2;
sbit	FP01 = 0xd0:1;
sbit	FP00 = 0xd0:0;
sfr	P1 = 0xd1;
sbit	FP17 = 0xd1:7;
sbit	FP16 = 0xd1:6;
sbit	FP15 = 0xd1:5;
sbit	FP14 = 0xd1:4;
sbit	FP13 = 0xd1:3;
sbit	FP12 = 0xd1:2;
sbit	FP11 = 0xd1:1;
sbit	FP10 = 0xd1:0;
sfr	P4 = 0xd4;
sbit	FP47 = 0xd4:7;
sbit	FP46 = 0xd4:6;
sbit	FP45 = 0xd4:5;
sbit	FP44 = 0xd4:4;
sbit	FP43 = 0xd4:3;
sbit	FP42 = 0xd4:2;
sbit	FP41 = 0xd4:1;
sbit	FP40 = 0xd4:0;
sfr	P5 = 0xd5;
sbit	FP57 = 0xd5:7;
sbit	FP56 = 0xd5:6;
sbit	FP55 = 0xd5:5;
sbit	FP54 = 0xd5:4;
sbit	FP53 = 0xd5:3;
sbit	FP52 = 0xd5:2;
sbit	FP51 = 0xd5:1;
sbit	FP50 = 0xd5:0;
sfr	T0M = 0xd8;
sbit	FT0ENB = 0xd8:7;
sbit	FT0RATE2 = 0xd8:6;
sbit	FT0RATE1 = 0xd8:5;
sbit	FT0RATE0 = 0xd8:4;
sbit	FT0TB = 0xd8:0;
sfr	T0C = 0xd9;
sfr	TC0M = 0xda;
sbit	FTC0ENB = 0xda:7;
sbit	FTC0RATE2 = 0xda:6;
sbit	FTC0RATE1 = 0xda:5;
sbit	FTC0RATE0 = 0xda:4;
sbit	FTC0CKS = 0xda:3;
sbit	FALOAD0 = 0xda:2;
sbit	FTC0OUT = 0xda:1;
sbit	FPWM0OUT = 0xda:0;
sfr	TC0C = 0xdb;
sfr	STKP = 0xdf;
sbit	FGIE = 0xdf:7;
sbit	FSTKPB2 = 0xdf:2;
sbit	FSTKPB1 = 0xdf:1;
sbit	FSTKPB0 = 0xdf:0;
sfr	P0UR = 0xe0;
sfr	P1UR = 0xe1;
sfr	P4UR = 0xe4;
sfr	P5UR = 0xe5;
sfr	_HL = 0xe6;
sfr	_YZ = 0xe7;
sfr	STK7L = 0xf0;
sfr	STK7H = 0xf1;
sfr	STK6L = 0xf2;
sfr	STK6H = 0xf3;
sfr	STK5L = 0xf4;
sfr	STK5H = 0xf5;
sfr	STK4L = 0xf6;
sfr	STK4H = 0xf7;
sfr	STK3L = 0xf8;
sfr	STK3H = 0xf9;
sfr	STK2L = 0xfa;
sfr	STK2H = 0xfb;
sfr	STK1L = 0xfc;
sfr	STK1H = 0xfd;
sfr	STK0L = 0xfe;
sfr	STK0H = 0xff;
#define SLEEPMODE __asm{SleepMode}
#define GREENMODE __asm{GreenMode}
#define SLOWMODE __asm{SlowMode}
#define SLOW2NORMAL __asm{Slow2Normal}
#endif
