#ifndef __SN8P27411A__H
#define __SN8P27411A__H

void _ClearWatchDogTimer(void);
void _ClrRAM(void);

#define NOP(X)  	__asm{	_NOP X }
#define LOG(X)  	__asm{	LOG CNameToAsmLabel(X) }
sfr	L = 0x80;
sfr	H = 0x81;
sfr	R = 0x82;
sfr	Z = 0x83;
sfr	Y = 0x84;
sfr	PFLAG = 0x86;
sbit	FZ = 0x86:0;
sbit	FDC = 0x86:1;
sbit	FC = 0x86:2;
sbit	FNPD = 0x86:6;
sbit	FNT0 = 0x86:7;
sfr	RBANK = 0x87;
sbit	FRBNKS0 = 0x87:0;
sfr	CMDB0 = 0x99;
sbit	FCM0DY3 = 0x99:7;
sbit	FCM0DY2 = 0x99:6;
sbit	FCM0DY1 = 0x99:5;
sbit	FCM0DY0 = 0x99:4;
sbit	FCM0D3 = 0x99:3;
sbit	FCM0D2 = 0x99:2;
sbit	FCM0D1 = 0x99:1;
sbit	FCM0D0 = 0x99:0;
sfr	CMDB1 = 0x9a;
sbit	FCM1REF = 0x9a:2;
sbit	FCM1D1 = 0x9a:1;
sbit	FCM1D0 = 0x9a:0;
sfr	CMDB2 = 0x9b;
sbit	FPWS1 = 0x9b:5;
sbit	FPWS0 = 0x9b:4;
sbit	FCM2REF = 0x9b:3;
sbit	FCM2NS = 0x9b:2;
sbit	FCM2D1 = 0x9b:1;
sbit	FCM2D0 = 0x9b:0;
sfr	CM0M = 0x9c;
sbit	FCM0EN = 0x9c:7;
sbit	FCM0OEN = 0x9c:6;
sbit	FCM0OUT = 0x9c:5;
sbit	FCM0SF = 0x9c:4;
sbit	FCM0G = 0x9c:3;
sbit	FCM0CLK = 0x9c:2;
sfr	CM1M = 0x9d;
sbit	FCM1EN = 0x9d:7;
sbit	FCM1OEN = 0x9d:6;
sbit	FCM1OUT = 0x9d:5;
sbit	FCM1SF = 0x9d:4;
sbit	FCM1G = 0x9d:3;
sbit	FCM1RS2 = 0x9d:2;
sbit	FCM1RS1 = 0x9d:1;
sbit	FCM1RS0 = 0x9d:0;
sfr	CM2M = 0x9e;
sbit	FCM2EN = 0x9e:7;
sbit	FCM2OEN = 0x9e:6;
sbit	FCM2OUT = 0x9e:5;
sbit	FCM2SF = 0x9e:4;
sbit	FCM2G = 0x9e:3;
sbit	FCM2RS2 = 0x9e:2;
sbit	FCM2RS1 = 0x9e:1;
sbit	FCM2RS0 = 0x9e:0;
sfr	OPM = 0x9f;
sbit	FOPPSW = 0x9f:1;
sbit	FOPEN = 0x9f:0;
sfr	T1M = 0xa0;
sbit	FT1ENB = 0xa0:7;
sbit	FT1RATE2 = 0xa0:6;
sbit	FT1RATE1 = 0xa0:5;
sbit	FT1RATE0 = 0xa0:4;
sbit	FT1SF = 0xa0:0;
sfr	T1C = 0xa1;
sfr	T1R = 0xa2;
sfr	T2M = 0xa3;
sbit	FT2ENB = 0xa3:7;
sbit	FT2RATE2 = 0xa3:6;
sbit	FT2RATE1 = 0xa3:5;
sbit	FT2RATE0 = 0xa3:4;
sbit	FT2SF = 0xa3:0;
sfr	T2C = 0xa4;
sfr	T2R = 0xa5;
sfr	P4CON = 0xae;
sfr	CMCON = 0xaf;
sfr	ADM = 0xB1;
sbit	FADENB = 0xB1:7;
sbit	FADS = 0xB1:6;
sbit	FEOC = 0xB1:5;
sbit	FGCHS = 0xB1:4;
sbit	FADREF = 0xB1:3;
sbit	FCHS2 = 0xB1:2;
sbit	FCHS1 = 0xB1:1;
sbit	FCHS0 = 0xB1:0;
sfr	ADB = 0xb2;
sfr	ADR = 0xb3;
sbit	FINTR4V = 0xb3:7;
sbit	FADCKS1 = 0xb3:6;
sbit	FADLEN = 0xb3:5;
sbit	FADCKS0 = 0xb3:4;
sbit	FADB3 = 0xb3:3;
sbit	FADB2 = 0xb3:2;
sbit	FADB1 = 0xb3:1;
sbit	FADB0 = 0xb3:0;
sfr	ADT = 0xb4;
sbit	FADTS1 = 0xb4:7;
sbit	FADTS0 = 0xb4:6;
sbit	FADT4 = 0xb4:4;
sbit	FADT3 = 0xb4:3;
sbit	FADT2 = 0xb4:2;
sbit	FADT1 = 0xb4:1;
sbit	FADT0 = 0xb4:0;
sfr	P0M = 0xb8;
sbit	FP05M = 0xb8:5;
sbit	FP04M = 0xb8:4;
sbit	FP03M = 0xb8:3;
sbit	FP02M = 0xb8:2;
sbit	FP00M = 0xb8:0;
sfr	PEDGE = 0xbf;
sbit	FP00G1 = 0xbf:1;
sbit	FP00G0 = 0xbf:0;
sfr	P4M = 0xc4;
sbit	FP47M = 0xc4:7;
sbit	FP46M = 0xc4:6;
sbit	FP45M = 0xc4:5;
sbit	FP44M = 0xc4:4;
sbit	FP43M = 0xc4:3;
sbit	FP42M = 0xc4:2;
sbit	FP41M = 0xc4:1;
sbit	FP40M = 0xc4:0;
sfr	INTRQ0 = 0xc8;
sbit	FADCIRQ = 0xc8:7;
sbit	FT1IRQ = 0xc8:6;
sbit	FTC0IRQ = 0xc8:5;
sbit	FT0IRQ = 0xc8:4;
sbit	FCM2IRQ = 0xc8:3;
sbit	FCM1IRQ = 0xc8:2;
sbit	FCM0IRQ = 0xc8:1;
sbit	FP00IRQ = 0xc8:0;
sfr	INTEN0 = 0xc9;
sbit	FADCIEN = 0xc9:7;
sbit	FT1IEN = 0xc9:6;
sbit	FTC0IEN = 0xc9:5;
sbit	FT0IEN = 0xc9:4;
sbit	FCM2IEN = 0xc9:3;
sbit	FCM1IEN = 0xc9:2;
sbit	FCM0IEN = 0xc9:1;
sbit	FP00IEN = 0xc9:0;
sfr	OSCM = 0xca;
sbit	FCPUM2 = 0xca:7;
sbit	FCPUM1 = 0xca:6;
sbit	FCPUM0 = 0xca:5;
sbit	FCLKMD1 = 0xca:4;
sbit	FCLKMD0 = 0xca:3;
sbit	FSTPHX2 = 0xca:2;
sbit	FSTPHX1 = 0xca:1;
sbit	FSTPHX0 = 0xca:0;
sfr	WDTR = 0xcc;
sfr	TC0R = 0xcd;
sfr	PCL = 0xce;
sfr	PCH = 0xcf;
sfr	P0 = 0xd0;
sbit	FP05 = 0xd0:5;
sbit	FP04 = 0xd0:4;
sbit	FP03 = 0xd0:3;
sbit	FP02 = 0xd0:2;
sbit	FP01 = 0xd0:1;
sbit	FP00 = 0xd0:0;
sfr	P4 = 0xd4;
sbit	FP47 = 0xd4:7;
sbit	FP46 = 0xd4:6;
sbit	FP45 = 0xd4:5;
sbit	FP44 = 0xd4:4;
sbit	FP43 = 0xd4:3;
sbit	FP42 = 0xd4:2;
sbit	FP41 = 0xd4:1;
sbit	FP40 = 0xd4:0;
sfr	INTRQ1 = 0xd6;
sbit	FT2IRQ = 0xd6:2;
sbit	FUTXIRQ = 0xd6:1;
sbit	FURXIRQ = 0xd6:0;
sfr	INTEN1 = 0xd7;
sbit	FT2IEN = 0xd7:2;
sbit	FUTXIEN = 0xd7:1;
sbit	FURXIEN = 0xd7:0;
sfr	T0M = 0xd8;
sbit	FT0ENB = 0xd8:7;
sbit	FT0RATE2 = 0xd8:6;
sbit	FT0RATE1 = 0xd8:5;
sbit	FT0RATE0 = 0xd8:4;
sfr	T0C = 0xd9;
sfr	TC0M = 0xda;
sbit	FTC0ENB = 0xda:7;
sbit	FTC0RATE2 = 0xda:6;
sbit	FTC0RATE1 = 0xda:5;
sbit	FTC0RATE0 = 0xda:4;
sbit	FTC0CKS = 0xda:3;
sbit	FTC0DIR = 0xda:2;
sbit	FTC0PO = 0xda:1;
sbit	FPWM0OUT = 0xda:0;
sfr	TC0C = 0xdb;
sfr	BZM = 0xdc;
sbit	FBZEN = 0xdc:7;
sbit	FBZRATE2 = 0xdc:6;
sbit	FBZRATE1 = 0xdc:5;
sfr	STKP = 0xdf;
sbit	FGIE = 0xdf:7;
sbit	FSTKPB2 = 0xdf:2;
sbit	FSTKPB1 = 0xdf:1;
sbit	FSTKPB0 = 0xdf:0;
sfr	P0UR = 0xe0;
sfr	P4UR = 0xe4;
sfr	_HL = 0xe6;
sfr	_YZ = 0xe7;
sfr	TC0D = 0xe8;
sfr	URTX = 0xe9;
sbit	FUTXEN = 0xe9:7;
sbit	FUTXPEN = 0xe9:6;
sbit	FUTXPS = 0xe9:5;
sbit	FUARTM = 0xe9:4;
sbit	FURXBZ = 0xe9:3;
sbit	FUTXBZ = 0xe9:2;
sbit	FUTXD8 = 0xe9:1;
sbit	FURXD8 = 0xe9:0;
sfr	URRX = 0xea;
sbit	FURXEN = 0xea:7;
sbit	FURXPEN = 0xea:6;
sbit	FURXPS = 0xea:5;
sbit	FURXPC = 0xea:4;
sbit	FUFMER = 0xea:3;
sbit	FURS2 = 0xea:2;
sbit	FURS1 = 0xea:1;
sbit	FURS0 = 0xea:0;
sfr	URCR = 0xeb;
sfr	UTXD = 0xec;
sfr	URXD = 0xed;
sfr	STK7L = 0xf0;
sfr	STK7H = 0xf1;
sfr	STK6L = 0xf2;
sfr	STK6H = 0xf3;
sfr	STK5L = 0xf4;
sfr	STK5H = 0xf5;
sfr	STK4L = 0xf6;
sfr	STK4H = 0xf7;
sfr	STK3L = 0xf8;
sfr	STK3H = 0xf9;
sfr	STK2L = 0xfa;
sfr	STK2H = 0xfb;
sfr	STK1L = 0xfc;
sfr	STK1H = 0xfd;
sfr	STK0L = 0xfe;
sfr	STK0H = 0xff;
#define SLEEPMODE __asm{SleepMode}
#define GREENMODE __asm{GreenMode}
#define SLOWMODE __asm{SlowMode}
#define SLOW2NORMAL __asm{Slow2Normal}
#endif
