#ifndef __SN8F22E84B__H
#define __SN8F22E84B__H

void _ClearWatchDogTimer(void);
void _ClrRAM(void);

#define NOP(X)  	__asm{	_NOP X }
#define LOG(X)  	__asm{	LOG CNameToAsmLabel(X) }
sfr	L = 0x80;
sfr	H = 0x81;
sfr	R = 0x82;
sfr	Z = 0x83;
sfr	Y = 0x84;
sfr	X = 0x85;
sfr	PFLAG = 0x86;
sbit	FZ = 0x86:0;
sbit	FDC = 0x86:1;
sbit	FC = 0x86:2;
sbit	FSTKOV = 0x86:4;
sbit	FRST = 0x86:5;
sbit	FWDT = 0x86:6;
sbit	FPOR = 0x86:7;
sfr	RBANK = 0x87;
sbit	FRBNKS0 = 0x87:0;
sbit	FRBNKS1 = 0x87:1;
sbit	FRBNKS2 = 0x87:2;
sfr	W0 = 0x88;
sfr	W1 = 0x89;
sfr	W2 = 0x8a;
sfr	W3 = 0x8b;
sfr	W4 = 0x8c;
sfr	W5 = 0x8d;
sfr	W6 = 0x8e;
sfr	W7 = 0x8f;
sfr	_HL = 0x90;
sfr	_YZ = 0x91;
sfr	UPLL = 0x92;
sbit	FUPLLEN = 0x92:0;
sbit	FUPLLSRC0 = 0x92:1;
sbit	FUPLLSRC1 = 0x92:2;
sbit	FUPLLRDY = 0x92:3;
sbit	FEHSRDY = 0x92:4;
sbit	FIHRC_EN = 0x92:5;
sbit	FEHS_EN = 0x92:6;
sfr	PCL = 0x93;
sfr	PCH = 0x94;
sfr	OSCM = 0x95;
sbit	FCPUM1 = 0x95:4;
sbit	FCPUM0 = 0x95:3;
sbit	FCLKMD = 0x95:2;
sbit	FSTPHX = 0x95:1;
sfr	WDTR = 0x96;
sfr	INTRQ0 = 0x97;
sbit	FWAKEIRQ = 0x97:0;
sbit	FP16IRQ = 0x97:1;
sbit	FP50IRQ = 0x97:2;
sbit	FUPDETIRQ = 0x97:3;
sbit	FUSBIRQ = 0x97:4;
sbit	FP0IRQ = 0x97:5;
sbit	FP1IRQ = 0x97:6;
sbit	FT0IRQ = 0x97:7;
sfr	INTRQ1 = 0x98;
sbit	FT1IRQ = 0x98:0;
sbit	FTC0IRQ = 0x98:1;
sbit	FTC1IRQ = 0x98:2;
sbit	FTC2IRQ = 0x98:3;
sbit	FNDTIRQ = 0x98:4;
sbit	FADCIRQ = 0x98:5;
sbit	FSIOIRQ = 0x98:6;
sfr	INTEN0 = 0x99;
sbit	FWAKEIEN = 0x99:0;
sbit	FP16IEN = 0x99:1;
sbit	FP50IEN = 0x99:2;
sbit	FUPDETIEN = 0x99:3;
sbit	FUSBIEN = 0x99:4;
sbit	FP0IEN = 0x99:5;
sbit	FP1IEN = 0x99:6;
sbit	FT0IEN = 0x99:7;
sfr	INTEN1 = 0x9a;
sbit	FT1IEN = 0x9a:0;
sbit	FTC0IEN = 0x9a:1;
sbit	FTC1IEN = 0x9a:2;
sbit	FTC2IEN = 0x9a:3;
sbit	FNDTIEN = 0x9a:4;
sbit	FADCIEN = 0x9a:5;
sbit	FSIOIEN = 0x9a:6;
sfr	P0W = 0x9b;
sbit	FP07W = 0x9b:7;
sbit	FP06W = 0x9b:6;
sbit	FP05W = 0x9b:5;
sbit	FP04W = 0x9b:4;
sbit	FP03W = 0x9b:3;
sbit	FP02W = 0x9b:2;
sbit	FP01W = 0x9b:1;
sbit	FP00W = 0x9b:0;
sfr	P1W = 0x9c;
sbit	FP17W = 0x9c:7;
sbit	FP15W = 0x9c:5;
sbit	FP14W = 0x9c:4;
sbit	FP13W = 0x9c:3;
sbit	FP12W = 0x9c:2;
sbit	FP11W = 0x9c:1;
sbit	FP10W = 0x9c:0;
sfr	P0IE = 0x9d;
sbit	FP07IE = 0x9d:7;
sbit	FP06IE = 0x9d:6;
sbit	FP05IE = 0x9d:5;
sbit	FP04IE = 0x9d:4;
sbit	FP03IE = 0x9d:3;
sbit	FP02IE = 0x9d:2;
sbit	FP01IE = 0x9d:1;
sbit	FP00IE = 0x9d:0;
sfr	P1IE = 0x9e;
sbit	FP17IE = 0x9e:7;
sbit	FP15IE = 0x9e:5;
sbit	FP14IE = 0x9e:4;
sbit	FP13IE = 0x9e:3;
sbit	FP12IE = 0x9e:2;
sbit	FP11IE = 0x9e:1;
sbit	FP10IE = 0x9e:0;
sfr	PEDGE = 0x9f;
sbit	FP16G0 = 0x9f:0;
sbit	FP16G1 = 0x9f:1;
sbit	FP50G0 = 0x9f:2;
sbit	FP50G1 = 0x9f:3;
sbit	FP20VSS_EN = 0x9f:5;
sbit	FUPDET_EN = 0x9f:6;
sbit	FUPDETS = 0x9f:7;
sfr	P0M = 0xa0;
sbit	FP00M = 0xa0:0;
sbit	FP01M = 0xa0:1;
sbit	FP02M = 0xa0:2;
sbit	FP03M = 0xa0:3;
sbit	FP04M = 0xa0:4;
sbit	FP05M = 0xa0:5;
sbit	FP06M = 0xa0:6;
sbit	FP07M = 0xa0:7;
sfr	P1M = 0xa1;
sbit	FP10M = 0xa1:0;
sbit	FP11M = 0xa1:1;
sbit	FP12M = 0xa1:2;
sbit	FP13M = 0xa1:3;
sbit	FP14M = 0xa1:4;
sbit	FP15M = 0xa1:5;
sbit	FP16M = 0xa1:6;
sbit	FP17M = 0xa1:7;
sfr	P2M = 0xa2;
sbit	FP21M = 0xa2:1;
sbit	FP22M = 0xa2:2;
sbit	FP23M = 0xa2:3;
sbit	FP24M = 0xa2:4;
sbit	FP25M = 0xa2:5;
sbit	FP26M = 0xa2:6;
sbit	FP27M = 0xa2:7;
sfr	P4M = 0xa3;
sbit	FP40M = 0xa3:0;
sbit	FP41M = 0xa3:1;
sbit	FP42M = 0xa3:2;
sbit	FP43M = 0xa3:3;
sbit	FP44M = 0xa3:4;
sbit	FP45M = 0xa3:5;
sbit	FP46M = 0xa3:6;
sbit	FP47M = 0xa3:7;
sfr	P5M = 0xa4;
sbit	FP50M = 0xa4:0;
sbit	FP51M = 0xa4:1;
sbit	FP52M = 0xa4:2;
sbit	FP53M = 0xa4:3;
sbit	FP54M = 0xa4:4;
sbit	FP55M = 0xa4:5;
sbit	FP56M = 0xa4:6;
sfr	P0 = 0xa5;
sbit	FP00 = 0xa5:0;
sbit	FP01 = 0xa5:1;
sbit	FP02 = 0xa5:2;
sbit	FP03 = 0xa5:3;
sbit	FP04 = 0xa5:4;
sbit	FP05 = 0xa5:5;
sbit	FP06 = 0xa5:6;
sbit	FP07 = 0xa5:7;
sfr	P1 = 0xa6;
sbit	FP10 = 0xa6:0;
sbit	FP11 = 0xa6:1;
sbit	FP12 = 0xa6:2;
sbit	FP13 = 0xa6:3;
sbit	FP14 = 0xa6:4;
sbit	FP15 = 0xa6:5;
sbit	FP16 = 0xa6:6;
sbit	FP17 = 0xa6:7;
sfr	P2 = 0xa7;
sbit	FP20 = 0xa7:0;
sbit	FP21 = 0xa7:1;
sbit	FP22 = 0xa7:2;
sbit	FP23 = 0xa7:3;
sbit	FP24 = 0xa7:4;
sbit	FP25 = 0xa7:5;
sbit	FP26 = 0xa7:6;
sbit	FP27 = 0xa7:7;
sfr	P4 = 0xa8;
sbit	FP40 = 0xa8:0;
sbit	FP41 = 0xa8:1;
sbit	FP42 = 0xa8:2;
sbit	FP43 = 0xa8:3;
sbit	FP44 = 0xa8:4;
sbit	FP45 = 0xa8:5;
sbit	FP46 = 0xa8:6;
sbit	FP47 = 0xa8:7;
sfr	P5 = 0xa9;
sbit	FP50 = 0xa9:0;
sbit	FP51 = 0xa9:1;
sbit	FP52 = 0xa9:2;
sbit	FP53 = 0xa9:3;
sbit	FP54 = 0xa9:4;
sbit	FP55 = 0xa9:5;
sbit	FP56 = 0xa9:6;
sfr	P0UR = 0xaa;
sfr	P1UR = 0xab;
sfr	P2UR = 0xac;
sfr	P4UR = 0xad;
sfr	P5UR = 0xae;
sfr	PECMD = 0xaf;
sfr	SIOM = 0xb0;
sbit	FSENB = 0xb0:7;
sbit	FSTART = 0xb0:6;
sbit	FSRATE1 = 0xb0:5;
sbit	FSRATE0 = 0xb0:4;
sbit	FMLSB = 0xb0:3;
sbit	FSCKMD = 0xb0:2;
sbit	FCPOL = 0xb0:1;
sbit	FCPHA = 0xb0:0;
sfr	SIOR = 0xb1;
sfr	SIOB = 0xb2;
sbit	FSIOB7 = 0xb2:7;
sbit	FSIOB6 = 0xb2:6;
sbit	FSIOB5 = 0xb2:5;
sbit	FSIOB4 = 0xb2:4;
sbit	FSIOB3 = 0xb2:3;
sbit	FSIOB2 = 0xb2:2;
sbit	FSIOB1 = 0xb2:1;
sbit	FSIOB0 = 0xb2:0;
sfr	T0M = 0xb3;
sbit	FT0ENB = 0xb3:7;
sbit	FT0RATE2 = 0xb3:6;
sbit	FT0RATE1 = 0xb3:5;
sbit	FT0RATE0 = 0xb3:4;
sfr	T0C = 0xb4;
sbit	FT0C7 = 0xb4:7;
sbit	FT0C6 = 0xb4:6;
sbit	FT0C5 = 0xb4:5;
sbit	FT0C4 = 0xb4:4;
sbit	FT0C3 = 0xb4:3;
sbit	FT0C2 = 0xb4:2;
sbit	FT0C1 = 0xb4:1;
sbit	FT0C0 = 0xb4:0;
sfr	T1M = 0xb5;
sbit	FT1ENB = 0xb5:7;
sbit	FT1RATE2 = 0xb5:6;
sbit	FT1RATE1 = 0xb5:5;
sbit	FT1RATE0 = 0xb5:4;
sbit	FT1CKS = 0xb5:3;
sbit	FT1ARC = 0xb5:2;
sbit	FT1G1 = 0xb5:1;
sbit	FT1G0 = 0xb5:0;
sfr	T1C_L = 0xb6;
sbit	FT1C7 = 0xb6:7;
sbit	FT1C6 = 0xb6:6;
sbit	FT1C5 = 0xb6:5;
sbit	FT1C4 = 0xb6:4;
sbit	FT1C3 = 0xb6:3;
sbit	FT1C2 = 0xb6:2;
sbit	FT1C1 = 0xb6:1;
sbit	FT1C0 = 0xb6:0;
sfr	T1C_H = 0xb7;
sbit	FT1C15 = 0xb7:7;
sbit	FT1C14 = 0xb7:6;
sbit	FT1C13 = 0xb7:5;
sbit	FT1C12 = 0xb7:4;
sbit	FT1C11 = 0xb7:3;
sbit	FT1C10 = 0xb7:2;
sbit	FT1C9 = 0xb7:1;
sbit	FT1C8 = 0xb7:0;
sfr	TC0M = 0xb8;
sbit	FTC0ENB = 0xb8:7;
sbit	FTC0RATE2 = 0xb8:6;
sbit	FTC0RATE1 = 0xb8:5;
sbit	FTC0RATE0 = 0xb8:4;
sbit	FTC0CKS1 = 0xb8:3;
sbit	FTC0CKS0 = 0xb8:2;
sbit	FTC0PO = 0xb8:1;
sbit	FPWM0OUT = 0xb8:0;
sfr	TC0C = 0xb9;
sfr	TC0R = 0xba;
sfr	TC0D = 0xbb;
sfr	TC1M = 0xbc;
sbit	FTC1ENB = 0xbc:7;
sbit	FTC1RATE2 = 0xbc:6;
sbit	FTC1RATE1 = 0xbc:5;
sbit	FTC1RATE0 = 0xbc:4;
sbit	FTC1CKS0 = 0xbc:2;
sbit	FTC1PO = 0xbc:1;
sbit	FPWM1OUT = 0xbc:0;
sfr	TC1C = 0xbd;
sfr	TC1R = 0xbe;
sfr	TC1D = 0xbf;
sfr	TC2M = 0xc0;
sbit	FTC2ENB = 0xc0:7;
sbit	FTC2RATE2 = 0xc0:6;
sbit	FTC2RATE1 = 0xc0:5;
sbit	FTC2RATE0 = 0xc0:4;
sbit	FTC2CKS0 = 0xc0:2;
sbit	FTC2PO = 0xc0:1;
sbit	FPWM2OUT = 0xc0:0;
sfr	TC2C = 0xc1;
sfr	TC2R = 0xc2;
sfr	TC2D = 0xc3;
sfr	PWCH = 0xc4;
sbit	FPWCH20 = 0xc4:5;
sbit	FPWCH21 = 0xc4:4;
sbit	FPWCH11 = 0xc4:3;
sbit	FPWCH10 = 0xc4:2;
sbit	FPWCH01 = 0xc4:1;
sbit	FPWCH00 = 0xc4:0;
sfr	PWES = 0xc5;
sbit	FPW2ES1 = 0xc5:3;
sbit	FPW2ES0 = 0xc5:2;
sbit	FPW1ES1 = 0xc5:1;
sbit	FPW1ES0 = 0xc5:0;
sfr	P2CON = 0xc6;
sbit	FP2CON7 = 0xc6:7;
sbit	FP2CON6 = 0xc6:6;
sbit	FP2CON5 = 0xc6:5;
sbit	FP2CON4 = 0xc6:4;
sbit	FP2CON3 = 0xc6:3;
sbit	FP2CON2 = 0xc6:2;
sbit	FP2CON1 = 0xc6:1;
sbit	FP2CON0 = 0xc6:0;
sfr	P4CON = 0xc7;
sbit	FP4CON7 = 0xc7:7;
sbit	FP4CON6 = 0xc7:6;
sbit	FP4CON5 = 0xc7:5;
sbit	FP4CON4 = 0xc7:4;
sbit	FP4CON3 = 0xc7:3;
sbit	FP4CON2 = 0xc7:2;
sbit	FP4CON1 = 0xc7:1;
sbit	FP4CON0 = 0xc7:0;
sfr	ADM = 0xc8;
sbit	FADENB = 0xc8:7;
sbit	FADS = 0xc8:6;
sbit	FEOC = 0xc8:5;
sbit	FGCHS = 0xc8:4;
sbit	FCHS3 = 0xc8:3;
sbit	FCHS2 = 0xc8:2;
sbit	FCHS1 = 0xc8:1;
sbit	FCHS0 = 0xc8:0;
sfr	ADB = 0xc9;
sbit	FADB11 = 0xc9:7;
sbit	FADB10 = 0xc9:6;
sbit	FADB9 = 0xc9:5;
sbit	FADB8 = 0xc9:4;
sbit	FADB7 = 0xc9:3;
sbit	FADB6 = 0xc9:2;
sbit	FADB5 = 0xc9:1;
sbit	FADB4 = 0xc9:0;
sfr	ADR = 0xca;
sbit	FAIN0IG_EN = 0xca:7;
sbit	FADCKS1 = 0xca:6;
sbit	FADLEN = 0xca:5;
sbit	FADCKS0 = 0xca:4;
sbit	FADB3 = 0xca:3;
sbit	FADB2 = 0xca:2;
sbit	FADB1 = 0xca:1;
sbit	FADB0 = 0xca:0;
sfr	ADT = 0xcb;
sbit	FADTS1 = 0xcb:7;
sbit	FADTS0 = 0xcb:6;
sbit	FEVHENB = 0xcb:5;
sbit	FADT4 = 0xcb:4;
sbit	FADT3 = 0xcb:3;
sbit	FADT2 = 0xcb:2;
sbit	FADT1 = 0xcb:1;
sbit	FADT0 = 0xcb:0;
sfr	UDA = 0xcc;
sbit	FUDE = 0xcc:7;
sbit	FUDA6 = 0xcc:6;
sbit	FUDA5 = 0xcc:5;
sbit	FUDA4 = 0xcc:4;
sbit	FUDA3 = 0xcc:3;
sbit	FUDA2 = 0xcc:2;
sbit	FUDA1 = 0xcc:1;
sbit	FUDA0 = 0xcc:0;
sfr	USTATUS = 0xcd;
sbit	FERR_TIMEOUT = 0xcd:7;
sbit	FERR_SETUP = 0xcd:6;
sbit	FEP0_PRESETUP = 0xcd:5;
sbit	FEP0_OUT_STALL = 0xcd:4;
sbit	FEP0_IN_STALL = 0xcd:3;
sbit	FEP0SETUP = 0xcd:2;
sbit	FEP0IN = 0xcd:1;
sbit	FEP0OUT = 0xcd:0;
sfr	USTATUS1 = 0xce;
sbit	FNDT2 = 0xce:7;
sbit	FNDT1 = 0xce:6;
sbit	FSOF = 0xce:4;
sbit	FBUS_RESUME = 0xce:3;
sbit	FBUS_WAKEUP = 0xce:2;
sbit	FBUS_RST = 0xce:1;
sbit	FSUSPEND = 0xce:0;
sfr	USB_INT_EN = 0xcf;
sbit	FSOF_IE = 0xcf:5;
sbit	FEPN_ACK_IE = 0xcf:4;
sbit	FEPN_NAK_IE = 0xcf:3;
sbit	FBUS_IE = 0xcf:2;
sbit	FBUSWK_IE = 0xcf:1;
sbit	FUSB_IE = 0xcf:0;
sfr	EP_ACK = 0xd0;
sbit	FEP6_ACK = 0xd0:5;
sbit	FEP5_ACK = 0xd0:4;
sbit	FEP4_ACK = 0xd0:3;
sbit	FEP3_ACK = 0xd0:2;
sbit	FEP2_ACK = 0xd0:1;
sbit	FEP1_ACK = 0xd0:0;
sfr	EP_NAK = 0xd1;
sbit	FEP6_NAK = 0xd1:5;
sbit	FEP5_NAK = 0xd1:4;
sbit	FEP4_NAK = 0xd1:3;
sbit	FEP3_NAK = 0xd1:2;
sbit	FEP2_NAK = 0xd1:1;
sbit	FEP1_NAK = 0xd1:0;
sfr	UCFG = 0xd2;
sbit	FULVD36_EN = 0xd2:7;
sbit	FVREG33_EN = 0xd2:6;
sbit	FPHY_EN = 0xd2:5;
sbit	FDPPU_EN = 0xd2:4;
sbit	FESD_EN = 0xd2:3;
sbit	FUSGIG_EN = 0xd2:2;
sbit	FVREG33DIS_EN = 0xd2:1;
sbit	FUSBRAM_EN = 0xd2:0;
sfr	UEPDIR = 0xd3;
sbit	FUE6D = 0xd3:5;
sbit	FUE5D = 0xd3:4;
sbit	FUE4D = 0xd3:3;
sbit	FUE3D = 0xd3:2;
sbit	FUE2D = 0xd3:1;
sbit	FUE1D = 0xd3:0;
sfr	UEPISO = 0xd4;
sbit	FUE6ISO = 0xd4:5;
sbit	FUE5ISO = 0xd4:4;
sbit	FUE4ISO = 0xd4:3;
sbit	FUE3ISO = 0xd4:2;
sbit	FUE2ISO = 0xd4:1;
sbit	FUE1ISO = 0xd4:0;
sfr	UE0R = 0xd5;
sbit	FUE0E = 0xd5:7;
sbit	FUE0M1 = 0xd5:6;
sbit	FUE0M0 = 0xd5:5;
sbit	FOUT_STALL_EN = 0xd5:4;
sbit	FIN_STALL_EN = 0xd5:3;
sfr	UE0R_C = 0xd6;
sbit	FUE0C6 = 0xd6:6;
sbit	FUE0C5 = 0xd6:5;
sbit	FUE0C4 = 0xd6:4;
sbit	FUE0C3 = 0xd6:3;
sbit	FUE0C2 = 0xd6:2;
sbit	FUE0C1 = 0xd6:1;
sbit	FUE0C0 = 0xd6:0;
sfr	UE1R = 0xd7;
sbit	FUE1E = 0xd7:7;
sbit	FUE1M1 = 0xd7:6;
sbit	FUE1M0 = 0xd7:5;
sfr	UE1R_C = 0xd8;
sbit	FUE1C7 = 0xd8:7;
sbit	FUE1C6 = 0xd8:6;
sbit	FUE1C5 = 0xd8:5;
sbit	FUE1C4 = 0xd8:4;
sbit	FUE1C3 = 0xd8:3;
sbit	FUE1C2 = 0xd8:2;
sbit	FUE1C1 = 0xd8:1;
sbit	FUE1C0 = 0xd8:0;
sfr	UE2R = 0xd9;
sbit	FUE2E = 0xd9:7;
sbit	FUE2M1 = 0xd9:6;
sbit	FUE2M0 = 0xd9:5;
sfr	UE2R_C = 0xda;
sbit	FUE2C7 = 0xda:7;
sbit	FUE2C6 = 0xda:6;
sbit	FUE2C5 = 0xda:5;
sbit	FUE2C4 = 0xda:4;
sbit	FUE2C3 = 0xda:3;
sbit	FUE2C2 = 0xda:2;
sbit	FUE2C1 = 0xda:1;
sbit	FUE2C0 = 0xda:0;
sfr	UE3R = 0xdb;
sbit	FUE3E = 0xdb:7;
sbit	FUE3M1 = 0xdb:6;
sbit	FUE3M0 = 0xdb:5;
sfr	UE3R_C = 0xdc;
sbit	FUE3C7 = 0xdc:7;
sbit	FUE3C6 = 0xdc:6;
sbit	FUE3C5 = 0xdc:5;
sbit	FUE3C4 = 0xdc:4;
sbit	FUE3C3 = 0xdc:3;
sbit	FUE3C2 = 0xdc:2;
sbit	FUE3C1 = 0xdc:1;
sbit	FUE3C0 = 0xdc:0;
sfr	UE4R = 0xdd;
sbit	FUE4E = 0xdd:7;
sbit	FUE4M1 = 0xdd:6;
sbit	FUE4M0 = 0xdd:5;
sfr	UE4R_C = 0xde;
sbit	FUE4C7 = 0xde:7;
sbit	FUE4C6 = 0xde:6;
sbit	FUE4C5 = 0xde:5;
sbit	FUE4C4 = 0xde:4;
sbit	FUE4C3 = 0xde:3;
sbit	FUE4C2 = 0xde:2;
sbit	FUE4C1 = 0xde:1;
sbit	FUE4C0 = 0xde:0;
sfr	UE5R = 0xdf;
sbit	FUE5E = 0xdf:7;
sbit	FUE5M1 = 0xdf:6;
sbit	FUE5M0 = 0xdf:5;
sfr	UE5R_C = 0xe0;
sbit	FUE5C7 = 0xe0:7;
sbit	FUE5C6 = 0xe0:6;
sbit	FUE5C5 = 0xe0:5;
sbit	FUE5C4 = 0xe0:4;
sbit	FUE5C3 = 0xe0:3;
sbit	FUE5C2 = 0xe0:2;
sbit	FUE5C1 = 0xe0:1;
sbit	FUE5C0 = 0xe0:0;
sfr	UE6R = 0xe1;
sbit	FUE6E = 0xe1:7;
sbit	FUE6M1 = 0xe1:6;
sbit	FUE6M0 = 0xe1:5;
sfr	UE6R_C = 0xe2;
sbit	FUE6C7 = 0xe2:7;
sbit	FUE6C6 = 0xe2:6;
sbit	FUE6C5 = 0xe2:5;
sbit	FUE6C4 = 0xe2:4;
sbit	FUE6C3 = 0xe2:3;
sbit	FUE6C2 = 0xe2:2;
sbit	FUE6C1 = 0xe2:1;
sbit	FUE6C0 = 0xe2:0;
sfr	UPID = 0xe3;
sbit	FUBDE = 0xe3:2;
sbit	FDDP = 0xe3:1;
sbit	FDDN = 0xe3:0;
sfr	UFRMNO_L = 0xe4;
sfr	UFRMNO_H = 0xe5;
sfr	PHYPRM = 0xe6;
sbit	PHYPRM_EN = 0xe6:7;
sfr	UTOGGLE = 0xe8;
sbit	FEP6_DATA01 = 0xe8:5;
sbit	FEP5_DATA01 = 0xe8:4;
sbit	FEP4_DATA01 = 0xe8:3;
sbit	FEP3_DATA01 = 0xe8:2;
sbit	FEP2_DATA01 = 0xe8:1;
sbit	FEP1_DATA01 = 0xe8:0;
sfr	EP2FIFO_ADDR = 0xe9;
sbit	FEP2FIFO7 = 0xe9:7;
sbit	FEP2FIFO6 = 0xe9:6;
sbit	FEP2FIFO5 = 0xe9:5;
sbit	FEP2FIFO4 = 0xe9:4;
sbit	FEP2FIFO3 = 0xe9:3;
sbit	FEP2FIFO2 = 0xe9:2;
sbit	FEP2FIFO1 = 0xe9:1;
sbit	FEP2FIFO0 = 0xe9:0;
sfr	EP3FIFO_ADDR = 0xea;
sbit	FEP3FIFO7 = 0xea:7;
sbit	FEP3FIFO6 = 0xea:6;
sbit	FEP3FIFO5 = 0xea:5;
sbit	FEP3FIFO4 = 0xea:4;
sbit	FEP3FIFO3 = 0xea:3;
sbit	FEP3FIFO2 = 0xea:2;
sbit	FEP3FIFO1 = 0xea:1;
sbit	FEP3FIFO0 = 0xea:0;
sfr	EP4FIFO_ADDR = 0xeb;
sbit	FEP4FIFO7 = 0xeb:7;
sbit	FEP4FIFO6 = 0xeb:6;
sbit	FEP4FIFO5 = 0xeb:5;
sbit	FEP4FIFO4 = 0xeb:4;
sbit	FEP4FIFO3 = 0xeb:3;
sbit	FEP4FIFO2 = 0xeb:2;
sbit	FEP4FIFO1 = 0xeb:1;
sbit	FEP4FIFO0 = 0xeb:0;
sfr	EP5FIFO_ADDR = 0xec;
sbit	FEP5FIFO7 = 0xec:7;
sbit	FEP5FIFO6 = 0xec:6;
sbit	FEP5FIFO5 = 0xec:5;
sbit	FEP5FIFO4 = 0xec:4;
sbit	FEP5FIFO3 = 0xec:3;
sbit	FEP5FIFO2 = 0xec:2;
sbit	FEP5FIFO1 = 0xec:1;
sbit	FEP5FIFO0 = 0xec:0;
sfr	EP6FIFO_ADDR = 0xed;
sbit	FEP6FIFO7 = 0xed:7;
sbit	FEP6FIFO6 = 0xed:6;
sbit	FEP6FIFO5 = 0xed:5;
sbit	FEP6FIFO4 = 0xed:4;
sbit	FEP6FIFO3 = 0xed:3;
sbit	FEP6FIFO2 = 0xed:2;
sbit	FEP6FIFO1 = 0xed:1;
sbit	FEP6FIFO0 = 0xed:0;
sfr	PS2M = 0xee;
sbit	FPS2ENB = 0xee:7;
sbit	FSDA = 0xee:3;
sbit	FSCK = 0xee:2;
sbit	FSDAM = 0xee:1;
sbit	FSCKM = 0xee:0;
sfr	STKP = 0xef;
sbit	FGIE = 0xef:7;
sbit	FLVD24 = 0xef:6;
sbit	FLVD33 = 0xef:5;
sbit	FULVD36 = 0xef:4;
sbit	FSTKPB2 = 0xef:2;
sbit	FSTKPB1 = 0xef:1;
sbit	FSTKPB0 = 0xef:0;
sfr	STK7L = 0xf0;
sfr	STK7H = 0xf1;
sfr	STK6L = 0xf2;
sfr	STK6H = 0xf3;
sfr	STK5L = 0xf4;
sfr	STK5H = 0xf5;
sfr	STK4L = 0xf6;
sfr	STK4H = 0xf7;
sfr	STK3L = 0xf8;
sfr	STK3H = 0xf9;
sfr	STK2L = 0xfa;
sfr	STK2H = 0xfb;
sfr	STK1L = 0xfc;
sfr	STK1H = 0xfd;
sfr	STK0L = 0xfe;
sfr	STK0H = 0xff;
#define SLEEPMODE __asm{SleepMode}
#define GREENMODE __asm{GreenMode}
#define SLOWMODE __asm{SlowMode}
#define SLOW2NORMAL __asm{Slow2Normal}
#define SET_P3_INPUT_PULLUP __asm{Set_P3_Input_Pullup}
#endif
