#ifndef __SN8P1929__H
#define __SN8P1929__H

void _ClearWatchDogTimer(void);
void _ClrRAM(void);

#define NOP(X)  	__asm{	_NOP X }
#define LOG(X)  	__asm{	LOG CNameToAsmLabel(X) }
sfr	L = 0x80;
sfr	H = 0x81;
sfr	R = 0x82;
sfr	Z = 0x83;
sfr	Y = 0x84;
sfr	X = 0x85;
sfr	PFLAG = 0x86;
sbit	FNT0 = 0x86:7;
sbit	FNPD = 0x86:6;
sbit	FC = 0x86:2;
sbit	FDC = 0x86:1;
sbit	FZ = 0x86:0;
sfr	RBANK = 0x87;
sbit	FRBNKS0 = 0x87:0;
sbit	FRBNKS1 = 0x87:1;
sbit	FRBNKS2 = 0x87:2;
sbit	FRBNKS3 = 0x87:3;
sfr	OPTION = 0x88;
sbit	FRCLK = 0x88:0;
#if ICE_Mode == 1
sfr	LCDM1 = 0XCB;
sbit	FLCDREF1 = 0XCB:7;
sbit	FLCDREF0 = 0XCB:6;
sbit	FLCDBNK = 0XCB:5;
sbit	FLCDENB = 0XCB:3;
sbit	FLCDBIAS = 0XCB:2;
#else
sfr	LCDM1 = 0x89;
sbit	FLCDREF1 = 0x89:7;
sbit	FLCDREF0 = 0x89:6;
sbit	FLCDBNK = 0x89:5;
sbit	FLCDENB = 0x89:3;
sbit	FLCDBIAS = 0x89:2;
#endif
sfr	AMPM = 0x90;
sbit	FCHPENB = 0x90:7;
sbit	FBGRENB = 0x90:6;
sbit	FFDS1 = 0x90:5;
sbit	FFDS0 = 0x90:4;
sbit	FGS2 = 0x90:3;
sbit	FGS1 = 0x90:2;
sbit	FGS0 = 0x90:1;
sbit	FAMPENB = 0x90:0;
sfr	AMPCHS = 0x91;
sbit	FCHS3 = 0x91:3;
sbit	FCHS2 = 0x91:2;
sbit	FCHS1 = 0x91:1;
sbit	FCHS0 = 0x91:0;
sfr	AMPCKS = 0x92;
sbit	FAMPCKS2 = 0x92:2;
sbit	FAMPCKS1 = 0x92:1;
sbit	FAMPCKS0 = 0x92:0;
sfr	ADCM = 0x93;
sbit	FIRVS = 0x93:3;
sbit	FRVS1 = 0x93:2;
sbit	FRVS0 = 0x93:1;
sbit	FADCENB = 0x93:0;
sfr	ADCKS = 0X94;
sfr	CPM = 0x95;
sbit	FACMENB = 0x95:7;
sbit	FAVDDRENB = 0x95:6;
sbit	FAVENB = 0x95:5;
sbit	FAVESEL1 = 0x95:4;
sbit	FAVESEL0 = 0x95:3;
sbit	FCPAUTO = 0x95:2;
sbit	FCPON = 0x95:1;
sbit	FCPRENB = 0x95:0;
sfr	CPCKS = 0x96;
sbit	FCPCKS3 = 0x96:3;
sbit	FCPCKS2 = 0x96:2;
sbit	FCPCKS1 = 0x96:1;
sbit	FCPCKS0 = 0x96:0;
sfr	DFM = 0x97;
sbit	FWRS0 = 0x97:2;
sbit	FDRDY = 0x97:0;
sfr	ADCDL = 0x98;
sfr	ADCDH = 0x99;
sfr	LBTM = 0x9A;
sbit	FLBTO = 0x9A:2;
sbit	FP41IO = 0x9A:1;
sbit	FLBTENB = 0x9A:0;
sfr	CPMTEST = 0x9B;
sbit	FCPSAVE = 0x9B:0;
#if ICE_Mode == 1
sfr	ROMADRH = 0XB4;
sbit	FVPPCHK = 0XB4:7;
sbit	FROMADR14 = 0XB4:6;
sbit	FROMADR13 = 0XB4:5;
sbit	FROMADR12 = 0XB4:4;
sbit	FROMADR11 = 0XB4:3;
sbit	FROMADR10 = 0XB4:2;
sbit	FROMADR9 = 0XB4:1;
sbit	FROMADR8 = 0XB4:0;
sfr	ROMADRL = 0XB6;
sbit	FROMADR7 = 0XB6:7;
sbit	FROMADR6 = 0XB6:6;
sbit	FROMADR5 = 0XB6:5;
sbit	FROMADR4 = 0XB6:4;
sbit	FROMADR3 = 0XB6:3;
sbit	FROMADR2 = 0XB6:2;
sbit	FROMADR1 = 0XB6:1;
sbit	FROMADR0 = 0XB6:0;
sfr	ROMDAH = 0XC7;
sbit	FROMDA15 = 0XC7:7;
sbit	FROMDA14 = 0XC7:6;
sbit	FROMDA13 = 0XC7:5;
sbit	FROMDA12 = 0XC7:4;
sbit	FROMDA11 = 0XC7:3;
sbit	FROMDA10 = 0XC7:2;
sbit	FROMDA9 = 0XC7:1;
sbit	FROMDA8 = 0XC7:0;
sfr	ROMDAL = 0XB0;
sbit	FROMDA7 = 0XB0:7;
sbit	FROMDA6 = 0XB0:6;
sbit	FROMDA5 = 0XB0:5;
sbit	FROMDA4 = 0XB0:4;
sbit	FROMDA3 = 0XB0:3;
sbit	FROMDA2 = 0XB0:2;
sbit	FROMDA1 = 0XB0:1;
sbit	FROMDA0 = 0XB0:0;
sfr	ROMCNT = 0XB5;
#else
sfr	ROMADRH = 0XA0;
sbit	FVPPCHK = 0XA0:7;
sbit	FROMADR14 = 0XA0:6;
sbit	FROMADR13 = 0XA0:5;
sbit	FROMADR12 = 0XA0:4;
sbit	FROMADR11 = 0XA0:3;
sbit	FROMADR10 = 0XA0:2;
sbit	FROMADR9 = 0XA0:1;
sbit	FROMADR8 = 0XA0:0;
sfr	ROMADRL = 0XA1;
sbit	FROMADR7 = 0XA1:7;
sbit	FROMADR6 = 0XA1:6;
sbit	FROMADR5 = 0XA1:5;
sbit	FROMADR4 = 0XA1:4;
sbit	FROMADR3 = 0XA1:3;
sbit	FROMADR2 = 0XA1:2;
sbit	FROMADR1 = 0XA1:1;
sbit	FROMADR0 = 0XA1:0;
sfr	ROMDAH = 0XA2;
sbit	FROMDA15 = 0XA2:7;
sbit	FROMDA14 = 0XA2:6;
sbit	FROMDA13 = 0XA2:5;
sbit	FROMDA12 = 0XA2:4;
sbit	FROMDA11 = 0XA2:3;
sbit	FROMDA10 = 0XA2:2;
sbit	FROMDA9 = 0XA2:1;
sbit	FROMDA8 = 0XA2:0;
sfr	ROMDAL = 0XA3;
sbit	FROMDA7 = 0XA3:7;
sbit	FROMDA6 = 0XA3:6;
sbit	FROMDA5 = 0XA3:5;
sbit	FROMDA4 = 0XA3:4;
sbit	FROMDA3 = 0XA3:3;
sbit	FROMDA2 = 0XA3:2;
sbit	FROMDA1 = 0XA3:1;
sbit	FROMDA0 = 0XA3:0;
sfr	ROMCNT = 0XA4;
#endif
sfr	PEDGE = 0xBF;
sbit	FPEDGEN = 0xBF:7;
sbit	FP00G1 = 0xBF:4;
sbit	FP00G0 = 0xBF:3;
sfr	P1W = 0xc0;
sbit	FP13W = 0xc0:3;
sbit	FP12W = 0xc0:2;
sbit	FP11W = 0xc0:1;
sbit	FP10W = 0xc0:0;
sfr	P1M = 0xC1;
sbit	FP13M = 0xC1:3;
sbit	FP12M = 0xC1:2;
sbit	FP11M = 0xC1:1;
sbit	FP10M = 0xC1:0;
sfr	P2M = 0xC2;
sbit	FP21M = 0xC2:1;
sbit	FP20M = 0xC2:0;
sfr	P4M = 0xC4;
sbit	FP42M = 0xC4:2;
sbit	FP41M = 0xC4:1;
sbit	FP40M = 0xC4:0;
sfr	P5M = 0xc5;
sbit	FP54M = 0xc5:4;
sbit	FP53M = 0xc5:3;
sbit	FP52M = 0xc5:2;
sbit	FP51M = 0xc5:1;
sbit	FP50M = 0xc5:0;
sfr	INTRQ = 0xc8;
sbit	FTC1IRQ = 0xc8:6;
sbit	FTC0IRQ = 0xc8:5;
sbit	FT0IRQ = 0xc8:4;
sbit	FP01IRQ = 0xc8:1;
sbit	FP00IRQ = 0xc8:0;
sfr	INTEN = 0xc9;
sbit	FTC1IEN = 0xc9:6;
sbit	FTC0IEN = 0xc9:5;
sbit	FT0IEN = 0xc9:4;
sbit	FP01IEN = 0xc9:1;
sbit	FP00IEN = 0xc9:0;
sfr	OSCM = 0xCA;
sbit	FWTCKS = 0xCA:7;
sbit	FWDRST = 0xCA:6;
sbit	FWDRATE = 0xCA:5;
sbit	FCPUM1 = 0xCA:4;
sbit	FCPUM0 = 0xCA:3;
sbit	FCLKMD = 0xCA:2;
sbit	FSTPHX = 0xCA:1;
sfr	TC0R = 0xCD;
sfr	PCL = 0xCE;
sfr	PCH = 0xCF;
sfr	P0 = 0xd0;
sbit	FP01 = 0xd0:1;
sbit	FP00 = 0xd0:0;
sfr	P1 = 0xD1;
sbit	FP13 = 0xD1:3;
sbit	FP12 = 0xD1:2;
sbit	FP11 = 0xD1:1;
sbit	FP10 = 0xD1:0;
sfr	P2 = 0xD2;
sbit	FP21 = 0xD2:1;
sbit	FP20 = 0xD2:0;
sfr	P4 = 0xD4;
sbit	FP42 = 0xD4:2;
sbit	FP41 = 0xD4:1;
sbit	FP40 = 0xD4:0;
sfr	P5 = 0xD5;
sbit	FP54 = 0xD5:4;
sbit	FP53 = 0xD5:3;
sbit	FP52 = 0xD5:2;
sbit	FP51 = 0xD5:1;
sbit	FP50 = 0xD5:0;
sfr	T0M = 0xD8;
sbit	FT0ENB = 0xD8:7;
sbit	FT0RATE2 = 0xD8:6;
sbit	FT0RATE1 = 0xD8:5;
sbit	FT0RATE0 = 0xD8:4;
sbit	FTC1X8 = 0xD8:3;
sbit	FTC0X8 = 0xD8:2;
sbit	FTC0GN = 0xD8:1;
sbit	FT0TB = 0xD8:0;
sfr	T0C = 0xD9;
sfr	TC0M = 0xda;
sbit	FTC0ENB = 0xda:7;
sbit	FTC0RATE2 = 0xda:6;
sbit	FTC0RATE1 = 0xda:5;
sbit	FTC0RATE0 = 0xda:4;
sbit	FTC0CKS = 0xda:3;
sbit	FALOAD0 = 0xda:2;
sbit	FTC0OUT = 0xda:1;
sbit	FPWM0OUT = 0xda:0;
sfr	TC0C = 0xDB;
sfr	TC1M = 0xDC;
sbit	FTC1ENB = 0xDC:7;
sbit	FTC1RATE2 = 0xDC:6;
sbit	FTC1RATE1 = 0xDC:5;
sbit	FTC1RATE0 = 0xDC:4;
sbit	FTC1CKS = 0xDC:3;
sbit	FALOAD1 = 0xDC:2;
sbit	FTC1OUT = 0xDC:1;
sbit	FPWM1OUT = 0xDC:0;
sfr	TC1C = 0xDD;
sfr	TC1R = 0xDE;
sfr	STKP = 0xDF;
sbit	FGIE = 0xDF:7;
sbit	FSTKPB3 = 0xDF:3;
sbit	FSTKPB2 = 0xDF:2;
sbit	FSTKPB1 = 0xDF:1;
sbit	FSTKPB0 = 0xDF:0;
sfr	P0UR = 0xE0;
sbit	FP01R = 0xE0:1;
sbit	FP00R = 0xE0:0;
sfr	P1UR = 0xE1;
sbit	FP13R = 0xE1:3;
sbit	FP12R = 0xE1:2;
sbit	FP11R = 0xE1:1;
sbit	FP10R = 0xE1:0;
sfr	P2UR = 0xE2;
sbit	FP21R = 0xE2:1;
sbit	FP20R = 0xE2:0;
sfr	P4UR = 0xE4;
sbit	FP42R = 0xE4:2;
sbit	FP41R = 0xE4:1;
sbit	FP40R = 0xE4:0;
sfr	P5UR = 0xE5;
sbit	FP54R = 0xE5:4;
sbit	FP53R = 0xE5:3;
sbit	FP52R = 0xE5:2;
sbit	FP51R = 0xE5:1;
sbit	FP50R = 0xE5:0;
sfr	_HL = 0xE6;
sfr	DP0X = 0xE6;
sfr	_YZ = 0xE7;
sfr	DP1X = 0xE7;
sfr	STK7L = 0xf0;
sfr	STK7H = 0xf1;
sfr	STK6L = 0xf2;
sfr	STK6H = 0xf3;
sfr	STK5L = 0xf4;
sfr	STK5H = 0xf5;
sfr	STK4L = 0xf6;
sfr	STK4H = 0xf7;
sfr	STK3L = 0xf8;
sfr	STK3H = 0xf9;
sfr	STK2L = 0xfa;
sfr	STK2H = 0xfb;
sfr	STK1L = 0xfc;
sfr	STK1H = 0xfd;
sfr	STK0L = 0xfe;
sfr	STK0H = 0xff;
#define SLEEPMODE __asm{SleepMode}
#define GREENMODE __asm{GreenMode}
#define SLOWMODE __asm{SlowMode}
#define SLOW2NORMAL __asm{Slow2Normal}
#if ICE_Mode == 1
sfr	P3M = 0xc3;
sbit	FP33M = 0xc3:3;
sbit	FP32M = 0xc3:2;
sbit	FP31M = 0xc3:1;
sbit	FP30M = 0xc3:0;
sfr	P3 = 0xD3;
sbit	FP33 = 0xD3:3;
sbit	FP32 = 0xD3:2;
sbit	FP31 = 0xD3:1;
sbit	FP30 = 0xD3:0;
sfr	P3UR = 0xE3;
sbit	FP33R = 0xE3:3;
sbit	FP32R = 0xE3:2;
sbit	FP31R = 0xE3:1;
sbit	FP30R = 0xE3:0;
#endif
#endif
