#ifndef __SN8P26L38__H
#define __SN8P26L38__H

void _ClearWatchDogTimer(void);
void _ClrRAM(void);

#define NOP(X)  	__asm{	_NOP X }
#define LOG(X)  	__asm{	LOG CNameToAsmLabel(X) }
sfr	L = 0x80;
sfr	H = 0x81;
sfr	R = 0x82;
sfr	Z = 0x83;
sfr	Y = 0x84;
sfr	PFLAG = 0x86;
sbit	FZ = 0x86:0;
sbit	FDC = 0x86:1;
sbit	FC = 0x86:2;
sbit	FLVD24 = 0x86:4;
sbit	FLVD28 = 0x86:5;
sbit	FNPD = 0x86:6;
sbit	FNT0 = 0x86:7;
sfr	RBANK = 0x87;
sbit	FBANKS0 = 0x87:0;
sbit	FBANKS1 = 0x87:1;
sbit	FBANKS2 = 0x87:2;
sfr	CMP0M = 0x9c;
sbit	FCMS0 = 0x9c:0;
sbit	FCMS1 = 0x9c:1;
sbit	FCM0OUT = 0x9c:2;
sbit	FCM0REF = 0x9c:3;
sbit	FCM0OEN = 0x9c:4;
sbit	FCM0IRQ = 0x9c:5;
sbit	FCM0IEN = 0x9c:6;
sbit	FCM0EN = 0x9c:7;
sfr	CMP1M = 0x9d;
sbit	FCM1OUT = 0x9d:2;
sbit	FCM1REF = 0x9d:3;
sbit	FCM1OEN = 0x9d:4;
sbit	FCM1IRQ = 0x9d:5;
sbit	FCM1IEN = 0x9d:6;
sbit	FCM1EN = 0x9d:7;
sfr	T1M = 0xa0;
sbit	FT1ENB = 0xa0:7;
sbit	FT1rate2 = 0xa0:6;
sbit	FT1rate1 = 0xa0:5;
sbit	FT1rate0 = 0xa0:4;
sfr	T1CL = 0xa1;
sfr	T1CH = 0xa2;
sfr	URTX = 0xa4;
sbit	FUTXEN = 0xa4:4;
sbit	FUTXPEN = 0xa4:3;
sbit	FUTXPS = 0xa4:2;
sbit	FUTXM = 0xa4:1;
sfr	URRX = 0xa5;
sbit	FURXEN = 0xa5:7;
sbit	FURXS1 = 0xa5:6;
sbit	FURXS0 = 0xa5:5;
sbit	FURXPEN = 0xa5:4;
sbit	FURXPS = 0xa5:3;
sbit	FURXPC = 0xa5:2;
sbit	FURXM = 0xa5:1;
sfr	URBRC = 0xa6;
sbit	FUDIV4 = 0xa6:7;
sbit	FUDIV3 = 0xa6:6;
sbit	FUDIV2 = 0xa6:5;
sbit	FUDIV1 = 0xa6:4;
sbit	FUDIV0 = 0xa6:3;
sbit	FUPCS2 = 0xa6:2;
sbit	FUPCS1 = 0xa6:1;
sbit	FUPCS0 = 0xa6:0;
sfr	URTXD1 = 0xa7;
sfr	URTXD2 = 0xa8;
sfr	URRXD1 = 0xa9;
sfr	URRXD2 = 0xaa;
sfr	SIOM = 0xb4;
sbit	FSENB = 0xb4:7;
sbit	FSTART = 0xb4:6;
sbit	FSRATE1 = 0xb4:5;
sbit	FSRATE0 = 0xb4:4;
sbit	FMLSB = 0xb4:3;
sbit	FSCKMD = 0xb4:2;
sbit	FCPOL = 0xb4:1;
sbit	FCPHA = 0xb4:0;
sfr	SIOR = 0xb5;
sfr	SIOB = 0xb6;
sfr	P0M = 0xb8;
sbit	FP00M = 0xb8:0;
sbit	FP01M = 0xb8:1;
sbit	FP03M = 0xb8:3;
sbit	FP04M = 0xb8:4;
sbit	FP05M = 0xb8:5;
sbit	FP06M = 0xb8:6;
sbit	FP07M = 0xb8:7;
sfr	PEDGE = 0xbf;
sbit	FP00G1 = 0xbf:4;
sbit	FP00G0 = 0xbf:3;
sfr	P1W = 0xc0;
sfr	P1M = 0xc1;
sbit	FP10M = 0xc1:0;
sbit	FP11M = 0xc1:1;
sbit	FP12M = 0xc1:2;
sbit	FP13M = 0xc1:3;
sbit	FP14M = 0xc1:4;
sbit	FP15M = 0xc1:5;
sbit	FP16M = 0xc1:6;
sbit	FP17M = 0xc1:7;
sfr	P2M = 0xc2;
sbit	FP20M = 0xc2:0;
sbit	FP21M = 0xc2:1;
sbit	FP22M = 0xc2:2;
sbit	FP23M = 0xc2:3;
sbit	FP24M = 0xc2:4;
sbit	FP25M = 0xc2:5;
sbit	FP26M = 0xc2:6;
sbit	FP27M = 0xc2:7;
sfr	P3M = 0xc3;
sbit	FP30M = 0xc3:0;
sbit	FP31M = 0xc3:1;
sbit	FP32M = 0xc3:2;
sbit	FP33M = 0xc3:3;
sfr	P4M = 0xc4;
sbit	FP40M = 0xc4:0;
sbit	FP41M = 0xc4:1;
sbit	FP42M = 0xc4:2;
sbit	FP43M = 0xc4:3;
sbit	FP44M = 0xc4:4;
sbit	FP45M = 0xc4:5;
sbit	FP46M = 0xc4:6;
sbit	FP47M = 0xc4:7;
sfr	P5M = 0xc5;
sbit	FP50M = 0xc5:0;
sbit	FP51M = 0xc5:1;
sbit	FP52M = 0xc5:2;
sbit	FP53M = 0xc5:3;
sbit	FP54M = 0xc5:4;
sbit	FP55M = 0xc5:5;
sbit	FP56M = 0xc5:6;
sbit	FP57M = 0xc5:7;
sfr	INTRQ = 0xc8;
sbit	FP00IRQ = 0xc8:0;
sbit	FP01IRQ = 0xc8:1;
sbit	FTXIRQ = 0xc8:2;
sbit	FRXIRQ = 0xc8:3;
sbit	FT0IRQ = 0xc8:4;
sbit	FT1IRQ = 0xc8:5;
sbit	FTC1IRQ = 0xc8:6;
sbit	FSIOIRQ = 0xc8:7;
sfr	INTEN = 0xc9;
sbit	FP00IEN = 0xc9:0;
sbit	FP01IEN = 0xc9:1;
sbit	FTXIEN = 0xc9:2;
sbit	FRXIEN = 0xc9:3;
sbit	FT0IEN = 0xc9:4;
sbit	FT1IEN = 0xc9:5;
sbit	FTC1IEN = 0xc9:6;
sbit	FSIOIEN = 0xc9:7;
sfr	OSCM = 0xca;
sbit	FCPUM1 = 0xca:4;
sbit	FCPUM0 = 0xca:3;
sbit	FCLKMD = 0xca:2;
sbit	FSTPHX = 0xca:1;
sfr	WDTR = 0xcc;
sfr	IRR = 0xcd;
sfr	PCL = 0xce;
sfr	PCH = 0xcf;
sfr	P0 = 0xd0;
sbit	FP00 = 0xd0:0;
sbit	FP01 = 0xd0:1;
sbit	FP02 = 0xd0:2;
sbit	FP03 = 0xd0:3;
sbit	FP04 = 0xd0:4;
sbit	FP05 = 0xd0:5;
sbit	FP06 = 0xd0:6;
sbit	FP07 = 0xd0:7;
sfr	P1 = 0xd1;
sbit	FP10 = 0xd1:0;
sbit	FP11 = 0xd1:1;
sbit	FP12 = 0xd1:2;
sbit	FP13 = 0xd1:3;
sbit	FP14 = 0xd1:4;
sbit	FP15 = 0xd1:5;
sbit	FP16 = 0xd1:6;
sbit	FP17 = 0xd1:7;
sfr	P2 = 0xd2;
sbit	FP20 = 0xd2:0;
sbit	FP21 = 0xd2:1;
sbit	FP22 = 0xd2:2;
sbit	FP23 = 0xd2:3;
sbit	FP24 = 0xd2:4;
sbit	FP25 = 0xd2:5;
sbit	FP26 = 0xd2:6;
sbit	FP27 = 0xd2:7;
sfr	P3 = 0xd3;
sbit	FP30 = 0xd3:0;
sbit	FP31 = 0xd3:1;
sbit	FP32 = 0xd3:2;
sbit	FP33 = 0xd3:3;
sfr	P4 = 0xd4;
sbit	FP40 = 0xd4:0;
sbit	FP41 = 0xd4:1;
sbit	FP42 = 0xd4:2;
sbit	FP43 = 0xd4:3;
sbit	FP44 = 0xd4:4;
sbit	FP45 = 0xd4:5;
sbit	FP46 = 0xd4:6;
sbit	FP47 = 0xd4:7;
sfr	P5 = 0xd5;
sbit	FP50 = 0xd5:0;
sbit	FP51 = 0xd5:1;
sbit	FP52 = 0xd5:2;
sbit	FP53 = 0xd5:3;
sbit	FP54 = 0xd5:4;
sbit	FP55 = 0xd5:5;
sbit	FP56 = 0xd5:6;
sbit	FP57 = 0xd5:7;
sfr	T0M = 0xd8;
sbit	FT0TB = 0xd8:0;
sbit	FT0RATE0 = 0xd8:4;
sbit	FT0RATE1 = 0xd8:5;
sbit	FT0RATE2 = 0xd8:6;
sbit	FT0ENB = 0xd8:7;
sfr	T0C = 0xd9;
sfr	IRM = 0xda;
sbit	FCREN = 0xda:0;
sbit	FIREN = 0xda:1;
sfr	IRC = 0xdb;
sfr	TC1M = 0xdc;
sbit	FTC1ENB = 0xdc:7;
sbit	FTC1RATE2 = 0xdc:6;
sbit	FTC1RATE1 = 0xdc:5;
sbit	FTC1RATE0 = 0xdc:4;
sbit	FTC1CKS = 0xdc:3;
sbit	FALOAD1 = 0xdc:2;
sbit	FTC1OUT = 0xdc:1;
sbit	FPWM1OUT = 0xdc:0;
sfr	TC1C = 0xdd;
sfr	TC1R = 0xde;
sfr	STKP = 0xdf;
sbit	FGIE = 0xdf:7;
sbit	FSTKPB2 = 0xdf:2;
sbit	FSTKPB1 = 0xdf:1;
sbit	FSTKPB0 = 0xdf:0;
sfr	P0UR = 0xe0;
sfr	P1UR = 0xe1;
sfr	P2UR = 0xe2;
sfr	P3UR = 0xe3;
sfr	P4UR = 0xe4;
sfr	P5UR = 0xe5;
sfr	_HL = 0xe6;
sfr	_YZ = 0xe7;
sfr	IRD = 0xe8;
sfr	P1OC = 0xe9;
sfr	STK7L = 0xf0;
sfr	STK7H = 0xf1;
sfr	STK6L = 0xf2;
sfr	STK6H = 0xf3;
sfr	STK5L = 0xf4;
sfr	STK5H = 0xf5;
sfr	STK4L = 0xf6;
sfr	STK4H = 0xf7;
sfr	STK3L = 0xf8;
sfr	STK3H = 0xf9;
sfr	STK2L = 0xfa;
sfr	STK2H = 0xfb;
sfr	STK1L = 0xfc;
sfr	STK1H = 0xfd;
sfr	STK0L = 0xfe;
sfr	STK0H = 0xff;
#define SLEEPMODE __asm{SleepMode}
#define GREENMODE __asm{GreenMode}
#define SLOWMODE __asm{SlowMode}
#define SLOW2NORMAL __asm{Slow2Normal}
#endif
