#ifndef __SN8F29E38__H
#define __SN8F29E38__H

void _ClearWatchDogTimer(void);
void _ClrRAM(void);

#define NOP(X)  	__asm{	_NOP X }
#define LOG(X)  	__asm{	LOG CNameToAsmLabel(X) }
sfr	L = 0x80;
sfr	H = 0x81;
sfr	R = 0x82;
sfr	Z = 0x83;
sfr	Y = 0x84;
sfr	X = 0x85;
sfr	PFLAG = 0x86;
sbit	FZ = 0x86:0;
sbit	FDC = 0x86:1;
sbit	FC = 0x86:2;
sfr	RBANK = 0x87;
sbit	FRBNKS0 = 0x87:0;
sbit	FRBNKS1 = 0x87:1;
sbit	FRBNKS2 = 0x87:2;
sbit	FRBNKS3 = 0x87:3;
sbit	FRBNKS4 = 0x87:4;
sfr	W0 = 0x88;
sfr	W1 = 0x89;
sfr	W2 = 0x8a;
sfr	W3 = 0x8b;
sfr	W4 = 0x8c;
sfr	W5 = 0x8d;
sfr	W6 = 0x8e;
sfr	W7 = 0x8f;
sfr	VREG = 0x90;
sbit	FVREFS = 0x90:0;
sbit	FAVDDRS0 = 0x90:2;
sbit	FAVDDRS1 = 0x90:3;
sbit	FAVDDREN = 0x90:4;
sbit	FAVEN = 0x90:5;
sbit	FACMEN = 0x90:6;
sbit	FBGEN = 0x90:7;
sfr	CHS = 0x91;
sbit	FMUXN0 = 0x91:0;
sbit	FMUXN1 = 0x91:1;
sbit	FMUXN2 = 0x91:2;
sbit	FMUXN3 = 0x91:3;
sbit	FMUXP0 = 0x91:4;
sbit	FMUXP1 = 0x91:5;
sbit	FMUXP2 = 0x91:6;
sbit	FMUXP3 = 0x91:7;
sfr	ADCM1 = 0x92;
sbit	FADCEN = 0x92:0;
sbit	FIRVS0 = 0x92:1;
sbit	FIRVS1 = 0x92:2;
sbit	FIRVS2 = 0x92:3;
sbit	FRVS = 0x92:4;
sbit	FOSR0 = 0x92:5;
sbit	FOSR1 = 0x92:6;
sbit	FOSR2 = 0x92:7;
sfr	ADCM2 = 0x93;
sbit	FDRDY = 0x93:0;
sbit	FADGN0 = 0x93:1;
sbit	FADGN1 = 0x93:2;
sbit	FGR = 0x93:3;
sbit	FGX = 0x93:4;
sbit	FINREN = 0x93:5;
sbit	FVDTEN = 0x93:6;
sbit	FUGBEN = 0x93:7;
sfr	ADCM3 = 0x94;
sbit	FADCKS0 = 0x94:0;
sbit	FADCKS1 = 0x94:1;
sbit	FADCKS2 = 0x94:2;
sbit	FADCKINV = 0x94:3;
sbit	FCPCSK0 = 0x94:5;
sbit	FCPCSK1 = 0x94:6;
sbit	FCPCKEN = 0x94:7;
sfr	LBTM = 0x95;
sbit	FLBTEN = 0x95:0;
sbit	FLBTO = 0x95:1;
sbit	FLBTDEL0 = 0x95:2;
sbit	FLBTDEL1 = 0x95:3;
sbit	FLBTDEL2 = 0x95:4;
sbit	FLBTDEL3 = 0x95:5;
sbit	FP11IO = 0x95:6;
sfr	LEDM = 0x96;
sbit	FLED1EN = 0x96:0;
sbit	FLED2EN = 0x96:1;
sbit	FLED3EN = 0x96:2;
sbit	FLED4EN = 0x96:3;
sbit	FLEDPW0 = 0x96:4;
sbit	FLEDPW1 = 0x96:5;
sbit	FLEDIO = 0x96:6;
sfr	DAM = 0x97;
sbit	FDAF0 = 0x97:0;
sbit	FDAF1 = 0x97:1;
sbit	FDAF2 = 0x97:2;
sbit	FDAEN = 0x97:7;
sfr	DABH = 0x98;
sbit	FDAB8 = 0x98:0;
sbit	FDAB9 = 0x98:1;
sbit	FDAB10 = 0x98:2;
sbit	FDAB11 = 0x98:3;
sfr	DABL = 0x99;
sbit	FDAB0 = 0x99:0;
sbit	FDAB1 = 0x99:1;
sbit	FDAB2 = 0x99:2;
sbit	FDAB3 = 0x99:3;
sbit	FDAB4 = 0x99:4;
sbit	FDAB5 = 0x99:5;
sbit	FDAB6 = 0x99:6;
sbit	FDAB7 = 0x99:7;
sfr	OPM1 = 0x9a;
sbit	FOP1EN = 0x9a:0;
sbit	FSW0 = 0x9a:2;
sbit	FSW1 = 0x9a:3;
sbit	FSW2 = 0x9a:4;
sbit	FSW3 = 0x9a:5;
sbit	FSW4 = 0x9a:6;
sbit	FSW5 = 0x9a:7;
sfr	OPM2 = 0x9b;
sbit	FSW6 = 0x9b:0;
sbit	FSW7 = 0x9b:1;
sbit	FSW8 = 0x9b:2;
sbit	FSW9 = 0x9b:3;
sbit	FSW10 = 0x9b:4;
sbit	FSW11 = 0x9b:5;
sfr	ADCDH = 0x9c;
sfr	ADCDM = 0x9d;
sfr	ADCDL = 0x9e;
sfr	AMPM = 0x9f;
sbit	FAMPEN = 0x9f:0;
sbit	FPCHPEN = 0x9f:1;
sbit	FGS0 = 0x9f:2;
sbit	FGS1 = 0x9f:3;
sbit	FGS2 = 0x9f:4;
sbit	FBGRCHPEN = 0x9f:6;
sbit	FBGRCMP = 0x9f:7;
sfr	P0M = 0xa0;
sbit	FP00M = 0xa0:0;
sbit	FP01M = 0xa0:1;
sbit	FP02M = 0xa0:2;
sbit	FP03M = 0xa0:3;
sbit	FP04M = 0xa0:4;
sbit	FP05M = 0xa0:5;
sbit	FP06M = 0xa0:6;
sbit	FP07M = 0xa0:7;
sfr	P1M = 0xa1;
sbit	FP10M = 0xa1:0;
sbit	FP11M = 0xa1:1;
sbit	FP12M = 0xa1:2;
sbit	FP13M = 0xa1:3;
sbit	FP14M = 0xa1:4;
sbit	FP15M = 0xa1:5;
sbit	FP16M = 0xa1:6;
sbit	FP17M = 0xa1:7;
sfr	P3M = 0xa2;
sbit	FP30M = 0xa2:0;
sbit	FP31M = 0xa2:1;
sbit	FP32M = 0xa2:2;
sbit	FP33M = 0xa2:3;
sbit	FP34M = 0xa2:4;
sbit	FP35M = 0xa2:5;
sfr	P5M = 0xa3;
sbit	FP50M = 0xa3:0;
sbit	FP51M = 0xa3:1;
sbit	FP52M = 0xa3:2;
sbit	FP53M = 0xa3:3;
sbit	FP54M = 0xa3:4;
sbit	FP55M = 0xa3:5;
sbit	FP56M = 0xa3:6;
sbit	FP57M = 0xa3:7;
sfr	P0UR = 0xa4;
sbit	FP00R = 0xa4:0;
sbit	FP01R = 0xa4:1;
sbit	FP02R = 0xa4:2;
sbit	FP03R = 0xa4:3;
sbit	FP04R = 0xa4:4;
sbit	FP05R = 0xa4:5;
sbit	FP06R = 0xa4:6;
sbit	FP07R = 0xa4:7;
sfr	P1UR = 0xa5;
sbit	FP10R = 0xa5:0;
sbit	FP11R = 0xa5:1;
sbit	FP12R = 0xa5:2;
sbit	FP13R = 0xa5:3;
sbit	FP14R = 0xa5:4;
sbit	FP15R = 0xa5:5;
sbit	FP16R = 0xa5:6;
sbit	FP17R = 0xa5:7;
sfr	P3UR = 0xa6;
sbit	FP30R = 0xa6:0;
sbit	FP31R = 0xa6:1;
sbit	FP32R = 0xa6:2;
sbit	FP33R = 0xa6:3;
sbit	FP34R = 0xa6:4;
sbit	FP35R = 0xa6:5;
sfr	P5UR = 0xa7;
sbit	FP50R = 0xa7:0;
sbit	FP51R = 0xa7:1;
sbit	FP52R = 0xa7:2;
sbit	FP53R = 0xa7:3;
sbit	FP54R = 0xa7:4;
sbit	FP55R = 0xa7:5;
sbit	FP56R = 0xa7:6;
sbit	FP57R = 0xa7:7;
sfr	P0 = 0xa8;
sbit	FP00 = 0xa8:0;
sbit	FP01 = 0xa8:1;
sbit	FP02 = 0xa8:2;
sbit	FP03 = 0xa8:3;
sbit	FP04 = 0xa8:4;
sbit	FP05 = 0xa8:5;
sbit	FP06 = 0xa8:6;
sbit	FP07 = 0xa8:7;
sfr	P1 = 0xa9;
sbit	FP10 = 0xa9:0;
sbit	FP11 = 0xa9:1;
sbit	FP12 = 0xa9:2;
sbit	FP13 = 0xa9:3;
sbit	FP14 = 0xa9:4;
sbit	FP15 = 0xa9:5;
sbit	FP16 = 0xa9:6;
sbit	FP17 = 0xa9:7;
sfr	P3 = 0xaa;
sbit	FP30 = 0xaa:0;
sbit	FP31 = 0xaa:1;
sbit	FP32 = 0xaa:2;
sbit	FP33 = 0xaa:3;
sbit	FP34 = 0xaa:4;
sbit	FP35 = 0xaa:5;
sfr	P5 = 0xab;
sbit	FP50 = 0xab:0;
sbit	FP51 = 0xab:1;
sbit	FP52 = 0xab:2;
sbit	FP53 = 0xab:3;
sbit	FP54 = 0xab:4;
sbit	FP55 = 0xab:5;
sbit	FP56 = 0xab:6;
sbit	FP57 = 0xab:7;
sfr	P1W = 0xac;
sbit	FP10W = 0xac:0;
sbit	FP11W = 0xac:1;
sbit	FP12W = 0xac:2;
sbit	FP13W = 0xac:3;
sbit	FP14W = 0xac:4;
sbit	FP15W = 0xac:5;
sbit	FP16W = 0xac:6;
sbit	FP17W = 0xac:7;
sfr	LCDM1 = 0xad;
sbit	FLCDRATE = 0xad:1;
sbit	FLCDENB = 0xad:2;
sbit	FLCDMODE = 0xad:3;
sbit	FLCDBNK = 0xad:5;
sbit	FP3SEG = 0xad:6;
sbit	FLCDPENB = 0xad:7;
sfr	LCDM2 = 0xae;
sbit	FVCP0 = 0xae:0;
sbit	FVCP1 = 0xae:1;
sbit	FVCP2 = 0xae:2;
sbit	FDUTY0 = 0xae:3;
sbit	FDUTY1 = 0xae:4;
sbit	FBGM = 0xae:5;
sbit	FVAR0 = 0xae:6;
sbit	FVAR1 = 0xae:7;
sfr	P2 = 0xaf;
sbit	FP20 = 0xaf:0;
sbit	FP21 = 0xaf:1;
sbit	FP22 = 0xaf:2;
sbit	FP23 = 0xaf:3;
sfr	INTEN0 = 0xb0;
sbit	FP00IEN = 0xb0:0;
sbit	FP01IEN = 0xb0:1;
sbit	FUTXIEN = 0xb0:2;
sbit	FURXIEN = 0xb0:3;
sbit	FT0IEN = 0xb0:4;
sbit	FTC0IEN = 0xb0:5;
sbit	FTC1IEN = 0xb0:6;
sbit	FADCIEN = 0xb0:7;
sfr	INTEN1 = 0xb1;
sbit	FMSPIEN = 0xb1:0;
sbit	FT0MOD = 0xb1:1;
sfr	INTRQ0 = 0xb2;
sbit	FP00IRQ = 0xb2:0;
sbit	FP01IRQ = 0xb2:1;
sbit	FUTXIRQ = 0xb2:2;
sbit	FURXIRQ = 0xb2:3;
sbit	FT0IRQ = 0xb2:4;
sbit	FTC0IRQ = 0xb2:5;
sbit	FTC1IRQ = 0xb2:6;
sbit	FADCIRQ = 0xb2:7;
sfr	INTRQ1 = 0xb3;
sbit	FMSPIRQ = 0xb3:0;
sfr	P2UR = 0xb4;
sbit	FP20R = 0xb4:0;
sbit	FP21R = 0xb4:1;
sbit	FP22R = 0xb4:2;
sbit	FP23R = 0xb4:3;
sfr	P2M = 0xb5;
sbit	FP20M = 0xb5:0;
sbit	FP21M = 0xb5:1;
sbit	FP22M = 0xb5:2;
sbit	FP23M = 0xb5:3;
sfr	OSCM = 0xb6;
sbit	FSTPHX = 0xb6:1;
sbit	FCLKMD = 0xb6:2;
sbit	FCPUM0 = 0xb6:3;
sbit	FCPUM1 = 0xb6:4;
sfr	WDTR = 0xb7;
sfr	PCH = 0xb8;
sfr	PCL = 0xb9;
sfr	STKP = 0xba;
sbit	FSTKPB0 = 0xba:0;
sbit	FSTKPB1 = 0xba:1;
sbit	FSTKPB2 = 0xba:2;
sbit	FSTKPB3 = 0xba:3;
sbit	FGIE = 0xba:7;
sfr	PEDGE = 0xbb;
sbit	FP00G0 = 0xbb:0;
sbit	FP00G1 = 0xbb:1;
sbit	FP01G0 = 0xbb:2;
sbit	FP01G1 = 0xbb:3;
sfr	_HL = 0xbc;
sfr	_YZ = 0xbd;
sfr	SEC = 0xbe;
sbit	SEC0 = 0xbe:0;
sbit	SEC1 = 0xbe:1;
sbit	SEC2 = 0xbe:2;
sbit	SEC3 = 0xbe:3;
sbit	SEC4 = 0xbe:4;
sbit	SEC5 = 0xbe:5;
sfr	MIN = 0xbf;
sbit	MIN0 = 0xbf:0;
sbit	MIN1 = 0xbf:1;
sbit	MIN2 = 0xbf:2;
sbit	MIN3 = 0xbf:3;
sbit	MIN4 = 0xbf:4;
sbit	MIN5 = 0xbf:5;
sfr	T0M = 0xc0;
sbit	FT0TB = 0xc0:0;
sbit	FTC0GN = 0xc0:1;
sbit	FTC0X8 = 0xc0:2;
sbit	FTC1X8 = 0xc0:3;
sbit	FT0RATE0 = 0xc0:4;
sbit	FT0RATE1 = 0xc0:5;
sbit	FT0RATE2 = 0xc0:6;
sbit	FT0ENB = 0xc0:7;
sfr	T0C = 0xc1;
sfr	TC0M = 0xc2;
sbit	FPWM0OUT = 0xc2:1;
sbit	FTC0CKS0 = 0xc2:2;
sbit	FTC0CKS1 = 0xc2:3;
sbit	FTC0RATE0 = 0xc2:4;
sbit	FTC0RATE1 = 0xc2:5;
sbit	FTC0RATE2 = 0xc2:6;
sbit	FTC0ENB = 0xc2:7;
sfr	TC0RL = 0xc3;
sfr	TC0RH = 0xc4;
sfr	TC0CL = 0xc5;
sfr	TC0CH = 0xc6;
sfr	TC0DL = 0xc7;
sfr	TC0DH = 0xc8;
sfr	TC1M = 0xc9;
sbit	FPWM1OUT = 0xc9:1;
sbit	FTC1CKS0 = 0xc9:2;
sbit	FTC1CKS1 = 0xc9:3;
sbit	FTC1RATE0 = 0xc9:4;
sbit	FTC1RATE1 = 0xc9:5;
sbit	FTC1RATE2 = 0xc9:6;
sbit	FTC1ENB = 0xc9:7;
sfr	TC1RL = 0xca;
sfr	TC1RH = 0xcb;
sfr	TC1CL = 0xcc;
sfr	TC1CH = 0xcd;
sfr	TC1DL = 0xce;
sfr	TC1DH = 0xcf;
sfr	MSPSTAT = 0xd0;
sbit	FBF = 0xd0:0;
sbit	FRED_WRT = 0xd0:2;
sbit	FS = 0xd0:3;
sbit	FP = 0xd0:4;
sbit	FD_A = 0xd0:5;
sbit	FCKE = 0xd0:6;
sfr	MSPM1 = 0xd1;
sbit	FMSPC = 0xd1:0;
sbit	FMSPWK = 0xd1:2;
sbit	FSLRXCKP = 0xd1:3;
sbit	FCKP = 0xd1:4;
sbit	FMSPENB = 0xd1:5;
sbit	FMSPOV = 0xd1:6;
sbit	FWCOL = 0xd1:7;
sfr	MSPM2 = 0xd2;
sbit	FSEN = 0xd2:0;
sbit	FRSEN = 0xd2:1;
sbit	FPEN = 0xd2:2;
sbit	FRCEN = 0xd2:3;
sbit	FACKEN = 0xd2:4;
sbit	FACKDT = 0xd2:5;
sbit	FACKSTAT = 0xd2:6;
sbit	FGCEN = 0xd2:7;
sfr	MSPBUF = 0xd3;
sfr	MSPADR = 0xd4;
sfr	URTX = 0xd5;
sbit	FUTXBZ = 0xd5:2;
sbit	FURXBZ = 0xd5:3;
sbit	FUTXBRK = 0xd5:4;
sbit	FUTXPS = 0xd5:5;
sbit	FUTXPEN = 0xd5:6;
sbit	FUTXEN = 0xd5:7;
sfr	URRX = 0xd6;
sbit	FURS0 = 0xd6:0;
sbit	FURS1 = 0xd6:1;
sbit	FURS2 = 0xd6:2;
sbit	FUFMER = 0xd6:3;
sbit	FURXPC = 0xd6:4;
sbit	FURXPS = 0xd6:5;
sbit	FURXPEN = 0xd6:6;
sbit	FURXEN = 0xd6:7;
sfr	URCR = 0xd7;
sfr	UTXD = 0xd8;
sfr	URXD = 0xd9;
sfr	PECMD = 0xda;
sfr	PEROML = 0xdb;
sfr	PEROMH = 0xdc;
sfr	PERAML = 0xdd;
sfr	PERAMH = 0xde;
sfr	PERAMCNT = 0xdf;
sfr	STK0L = 0xe0;
sfr	STK0H = 0xe1;
sfr	STK1L = 0xe2;
sfr	STK1H = 0xe3;
sfr	STK2L = 0xe4;
sfr	STK2H = 0xe5;
sfr	STK3L = 0xe6;
sfr	STK3H = 0xe7;
sfr	STK4L = 0xe8;
sfr	STK4H = 0xe9;
sfr	STK5L = 0xea;
sfr	STK5H = 0xeb;
sfr	STK6L = 0xec;
sfr	STK6H = 0xed;
sfr	STK7L = 0xee;
sfr	STK7H = 0xef;
sfr	STK8L = 0xf0;
sfr	STK8H = 0xf1;
sfr	STK9L = 0xf2;
sfr	STK9H = 0xf3;
sfr	STK10L = 0xf4;
sfr	STK10H = 0xf5;
sfr	STK11L = 0xf6;
sfr	STK11H = 0xf7;
sfr	STK12L = 0xf8;
sfr	STK12H = 0xf9;
sfr	STK13L = 0xfa;
sfr	STK13H = 0xfb;
sfr	STK14L = 0xfc;
sfr	STK14H = 0xfd;
sfr	STK15L = 0xfe;
sfr	STK15H = 0xff;
#define SLEEPMODE __asm{SleepMode}
#define GREENMODE __asm{GreenMode}
#define SLOWMODE __asm{SlowMode}
#define SLOW2NORMAL __asm{Slow2Normal}
#endif
