
;------------------------------------------------------------------------------
;  CHIP: SN8P2613
;  Revision History
;  
;  V01   02/04/2005  1. First issue and only for SN8ICE 2K.
;
;  V02   04/01/2005  1. Remove Low_Power code option. 
;                    2. Remove LVD_MAX code option. LVD 3.6V only supports flag function
;                    3. Remove LVDB code option. LVD is no de-bounce selection. 
;                    4. Use Enable_ORG4_7 command to release ROM address 4~7
;
;  V03   06/30/2005  1. Modify Low_Power mode initial as disable. 
;
;  V04   12/12/2005  1. Remove 32K_X'tal and IHRC_RTC code options.
;					 2.	Remove T0TB bit of T0 RTC.
;  					 3. Limit Fcpu 1T, 2T rate when Noise_Filter enable.
;  V05   12/17/2007  1. "GreenMode","SleepMode","SlowMode","Slow2Normal" macro programs. 
;  V06   04/03/2008  1. Add "RedWrt_FORMAT    1"  	
;  V07   06/29/2010  1. modify MACRO text "SLowMode" to "SlowMode"
;------------------------------------------------------------------------------
.ASSEMBLY    RedWrt_FORMAT    1

.Assembly	INC_VER		7
.Assembly	ASM_FORMAT	1
.Assembly	RAM_Size	64

.Assembly	INSTRUMENT	SN8P2613
.Assembly	BIT_FILE	SN8P2613

.Assembly	OTP_BODY_SIZE	0x0800
.Assembly	USER_ROM_SIZE	0x07FC

;.Assembly	OTP_TEST_SIZE	0x00A0
;.Assembly	MASK_TEST_FILE	SN8A1602A
.Assembly	MASK_TEST_CODE	0x0000, 0x0000, 0x0000, 0x0000
;.Assembly	OTP_TEST_FILE	SN86P
.Assembly	PGM_TYPE	8
.Assembly	CHIP_ID		0x3210
.Assembly	command		Enable_ORG4_7, GREEN_NOP_LIMIT
.Assembly	Port_Pins	2, 8, 0, 0, 0, 8

; Code Option 0x7FF
.Assembly	OPTION		0		Noise_Filter	Disable	Enable
.Assembly	OPTION		1		Security	Enable	Disable
.Assembly	OPTION		2		Fcpu		Fosc/1 Fosc/2 Fosc/4 Fosc/8 x x x Fosc/16 
.Help
{
	Fcpu		: 	"Only Effective for HIGH Clock"
}
.Assembly	OPTION		5		High_Clk	IHRC_16M x x x Ext_RC x 12M_X'tal  4M_X'tal
.Help
{
	IHRC_16M	:	"Internal 16M RC Oscillator"
	Ext_RC		:	"Connect R to VDD and Xin\nConnect C to GND and Xin"
	12M_X'tal	:	"Crystal/Resonator: 10Mhz~16Mhz"
	4M_X'tal	:	"Crystal/Resonator: 2Mhz~10Mhz"
}
.Assembly	OPTION		8		Watch_Dog	Always_On x x x x Enable x x x x Disable x x x x x
.Assembly	OPTION		12		Reset_Pin   P15 	Reset
;.Assembly	OPTION		13		Rst_Length  No 128*ILRC
.Assembly	OPTION		13		Fix_High
;.Assembly	OPTION		14		Low_Power	Enabel Disable
.Assembly	OPTION		14		Fix_High
.Assembly	OPTION		15		Fix_Low

; Code Option 0x7FE
.Assembly	OPTION		16		Fix_Low
.Assembly	OPTION		17		Fix_High
.Assembly	OPTION		18		Fix_Low
.Assembly	OPTION		19		Fix_High
.Assembly	OPTION		20		Fix_High
.Assembly	OPTION		21		Fix_Low
.Assembly	OPTION		22		Fix_High
.Assembly	OPTION		23		Fix_Low
.Assembly	OPTION		24		Fix_Low
.Assembly	OPTION		25		Fix_High
.Assembly	OPTION		26		Fix_Low
.Assembly	OPTION		27		Fix_High
.Assembly	OPTION		28 : 31		Fix_High

; Code Option 0x7FD
.Assembly	OPTION		32 : 40		Fix_High

;.Assembly	OPTION		41		LVD     	LVD_MAX	LVD_H	LVD_M	LVD_L
.Assembly	OPTION		41		LVD     	x	LVD_H	LVD_M	LVD_L
.Help
{
	LVD_L		:	"2.0V Reset"
	LVD_M		:	"2.0V Reset\nEnable LVD24 bit of PFLAG for\n2.4V Low Voltage Indicator"
	LVD_H		:	"2.4V Reset\nEnable LVD36 bit of PFLAG for\n3.6V Low Voltage Indicator"	
;	LVD_MAX		:	"3.6V Reset"	
}

;.Assembly	OPTION		43	LVDB no 1024_ILRC 8_ILRC 32_ILRC
.Assembly	OPTION		43 : 44	Fix_High
.Assembly	OPTION		45 : 63	Fix_High

.Assembly	OPTION		2ffh

	R			EQU		82H
	Z			EQU		83H
	Y			EQU		84H
	
	PFLAG			EQU		86H
		FZ		EQU		PFLAG.0
		FDC		EQU		PFLAG.1
		FC		EQU		PFLAG.2
		FLVD24	EQU_R		PFLAG.4
		FLVD36	EQU_R		PFLAG.5
		FNPD	EQU		PFLAG.6
		FNT0	EQU		PFLAG.7

	P0M			EQU		0B8H
		FP00M	EQU		P0M.0
		FP01M	EQU		P0M.1

	PEDGE		EQU		0BFH		
		FP00G1	EQU		PEDGE.4
		FP00G0	EQU		PEDGE.3

	P1W			EQU_W	0C0H

	P1M			EQU		0C1H
		FP10M	EQU		P1M.0
		FP11M	EQU		P1M.1
		FP12M	EQU		P1M.2
		FP13M	EQU		P1M.3
		FP14M	EQU		P1M.4
		FP16M	EQU		P1M.6
		FP17M	EQU		P1M.7

	P5M			EQU		0C5H
  		FP50M	EQU		P5M.0
  		FP51M	EQU		P5M.1
  		FP52M	EQU		P5M.2
  		FP53M	EQU		P5M.3
  		FP54M	EQU		P5M.4
  		FP55M	EQU		P5M.5
  		FP56M	EQU		P5M.6
  		FP57M	EQU		P5M.7

	INTRQ		EQU		0C8H
		FP00IRQ	EQU		INTRQ.0
		FP01IRQ	EQU		INTRQ.1
		FT0IRQ	EQU		INTRQ.4
		FTC0IRQ	EQU		INTRQ.5

	INTEN		EQU		0C9H
		FP00IEN	EQU		INTEN.0
		FP01IEN	EQU		INTEN.1
		FT0IEN	EQU		INTEN.4
		FTC0IEN	EQU		INTEN.5

	OSCM		EQU		0CAH
		FCPUM1	EQU		OSCM.4
		FCPUM0	EQU		OSCM.3
		FCLKMD	EQU		OSCM.2
		FSTPHX	EQU		OSCM.1

	WDTR		EQU_W	0CCH

    TC0R        EQU_W   0CDH       

	PCL			EQU		0CEH
	PCH			EQU		0CFH

	P0			EQU 	0D0H
		FP00	EQU 	P0.0
		FP01	EQU 	P0.1

	P1			EQU 	0D1H
		FP10	EQU 	P1.0
		FP11	EQU 	P1.1
		FP12	EQU 	P1.2
		FP13	EQU 	P1.3
		FP14	EQU 	P1.4
		FP15	EQU_R 	P1.5
		FP16	EQU 	P1.6
		FP17	EQU 	P1.7

	P5			EQU		0D5H
		FP50	EQU		P5.0
		FP51	EQU		P5.1
		FP52	EQU		P5.2
		FP53	EQU		P5.3
		FP54	EQU		P5.4
		FP55	EQU		P5.5
		FP56	EQU		P5.6
		FP57	EQU		P5.7
		
	T0M			EQU		0D8H
		FT0RATE0   EQU	T0M.4
		FT0RATE1   EQU	T0M.5
		FT0RATE2   EQU	T0M.6
		FT0ENB     EQU	T0M.7

	T0C			EQU		0D9H

	TC0M		EQU		0DAH
		FTC0ENB		EQU	TC0M.7
		FTC0RATE2	EQU	TC0M.6
		FTC0RATE1	EQU	TC0M.5
		FTC0RATE0	EQU	TC0M.4
		FTC0CKS		EQU	TC0M.3
        FALOAD0     EQU TC0M.2
        FTC0OUT     EQU TC0M.1
        FPWM0OUT    EQU TC0M.0 

	TC0C		EQU		0DBH

	STKP		EQU		0DFH
		FGIE	EQU		STKP.7
		FSTKPB2	EQU		STKP.2
		FSTKPB1	EQU		STKP.1
		FSTKPB0	EQU		STKP.0

    P0UR        EQU_W     0E0H

    P1UR        EQU_W     0E1H

    P5UR        EQU_W     0E5H

	@YZ			EQU		0E7H

	P1OC		EQU_W	0E9H

	STK3L		EQU		0F8h
	STK3H		EQU		0F9h
	STK2L		EQU		0FAh
	STK2H		EQU		0FBh
	STK1L		EQU		0FCh
	STK1H		EQU		0FDh
	STK0L		EQU		0FEh
	STK0H		EQU		0FFh

; -----------------------------------------------------
; Clear watchdog macro for compatibility in S8KD-2 ICE
;  
; Total Cycle: 2 

	@RST_WDT	macro		
 		   MOV  A, #0x5A
		   B0MOV  WDTR, A
	endm
; -----------------------------------------------------
; Sleep Mode control macro for compatibility in S8KD-2 ICE
;  
; Total Cycle: 1

	SleepMode	macro	
		B0BSET	FCPUM0
	endm
; -----------------------------------------------------
; Green Mode control macro for compatibility in S8KD-2 ICE
;  
; Total Cycle: 3

	GreenMode	macro	
		B0BSET	FCPUM1
		NOP
		NOP
	endm
; -----------------------------------------------------
; Slow Mode control macro for compatibility in S8KD-2 ICE
;  
; Total Cycle: 2

	SlowMode	macro	
		B0BSET	FCLKMD
		B0BSET	FSTPHX
	endm
; -----------------------------------------------------
;  Slow mode to Normal Mode control macro for compatibility in S8KD-2 ICE
;  
; Total Cycle: 5

	Slow2Normal	macro	
		B0BCLR	FSTPHX
		NOP
		NOP
		NOP
		B0BCLR	FCLKMD
	endm
; -----------------------------------------------------	
	
.TEXT
{
	//{{SONIX_OPTION_RULE
	IF Noise_Filter == Enable
	{
		OPTION		2		Fcpu		x x Fosc/4 Fosc/8 x x x Fosc/16  
  	}
	ELSE	
	{
		OPTION		2		Fcpu		Fosc/1 Fosc/2 Fosc/4 Fosc/8 x x x Fosc/16  
  	}
	ENDP
	//}}SONIX_OPTION_RULE
}
