#ifndef __SN8P2242__H
#define __SN8P2242__H

void _ClearWatchDogTimer(void);
void _ClrRAM(void);

#define NOP(X)  	__asm{	_NOP X }
#define LOG(X)  	__asm{	LOG CNameToAsmLabel(X) }
sfr	R = 0x82;
sfr	Z = 0x83;
sfr	Y = 0x84;
sfr	PFLAG = 0x86;
sbit	FZ = 0x86:0;
sbit	FDC = 0x86:1;
sbit	FC = 0x86:2;
sbit	FNPD = 0x86:6;
sbit	FNT0 = 0x86:7;
sfr	UDA = 0x90;
sbit	FUDE = 0x90:7;
sbit	FUDA6 = 0x90:6;
sbit	FUDA5 = 0x90:5;
sbit	FUDA4 = 0x90:4;
sbit	FUDA3 = 0x90:3;
sbit	FUDA2 = 0x90:2;
sbit	FUDA1 = 0x90:1;
sbit	FUDA0 = 0x90:0;
sfr	USTATUS = 0x91;
sbit	FBUS_RST = 0x91:4;
sbit	FSUSPEND = 0x91:3;
sbit	FEP0_SETUP = 0x91:2;
sbit	FEP0_IN = 0x91:1;
sbit	FEP0_OUT = 0x91:0;
sfr	EP0OUT_CNT = 0x92;
sbit	FUEP0OC4 = 0x92:4;
sbit	FUEP0OC3 = 0x92:3;
sbit	FUEP0OC2 = 0x92:2;
sbit	FUEP0OC1 = 0x92:1;
sbit	FUEP0OC0 = 0x92:0;
sfr	USB_INT_EN = 0x93;
sbit	FREG_EN = 0x93:7;
sbit	FDN_PU_EN = 0x93:6;
sbit	FIHRCCTR_EN = 0x93:5;
sbit	FLENGTH4_TOGGLE = 0x93:0;
sfr	EP_ACK = 0x94;
sbit	FEP2_ACK = 0x94:1;
sbit	FEP1_ACK = 0x94:0;
sfr	UE0R = 0x96;
sbit	FUE0E = 0x96:7;
sbit	FUE0M1 = 0x96:6;
sbit	FUE0M0 = 0x96:5;
sbit	FUE0C3 = 0x96:3;
sbit	FUE0C2 = 0x96:2;
sbit	FUE0C1 = 0x96:1;
sbit	FUE0C0 = 0x96:0;
sfr	UE1R = 0x97;
sbit	FUE1E = 0x97:7;
sbit	FUE1M1 = 0x97:6;
sbit	FUE1M0 = 0x97:5;
sbit	FUE1D = 0x97:4;
sbit	FUE1C3 = 0x97:3;
sbit	FUE1C2 = 0x97:2;
sbit	FUE1C1 = 0x97:1;
sbit	FUE1C0 = 0x97:0;
sfr	UE2R = 0x98;
sbit	FUE2E = 0x98:7;
sbit	FUE2M1 = 0x98:6;
sbit	FUE2M0 = 0x98:5;
sbit	FUE2D = 0x98:4;
sbit	FUE2C3 = 0x98:3;
sbit	FUE2C2 = 0x98:2;
sbit	FUE2C1 = 0x98:1;
sbit	FUE2C0 = 0x98:0;
sfr	UDP0_L = 0xa3;
sbit	FUDP07 = 0xa3:7;
sbit	FUDP06 = 0xa3:6;
sbit	FUDP05 = 0xa3:5;
sbit	FUDP04 = 0xa3:4;
sbit	FUDP03 = 0xa3:3;
sbit	FUDP02 = 0xa3:2;
sbit	FUDP01 = 0xa3:1;
sbit	FUDP00 = 0xa3:0;
sfr	UDP0_H = 0xa4;
sbit	FWE0 = 0xa4:7;
sbit	FRE0 = 0xa4:6;
sfr	UDR0_R = 0xa5;
sbit	FUDR0_R7 = 0xa5:7;
sbit	FUDR0_R6 = 0xa5:6;
sbit	FUDR0_R5 = 0xa5:5;
sbit	FUDR0_R4 = 0xa5:4;
sbit	FUDR0_R3 = 0xa5:3;
sbit	FUDR0_R2 = 0xa5:2;
sbit	FUDR0_R1 = 0xa5:1;
sbit	FUDR0_R0 = 0xa5:0;
sfr	UDR0_W = 0xa6;
sbit	FUDR0_W7 = 0xa6:7;
sbit	FUDR0_W6 = 0xa6:6;
sbit	FUDR0_W5 = 0xa6:5;
sbit	FUDR0_W4 = 0xa6:4;
sbit	FUDR0_W3 = 0xa6:3;
sbit	FUDR0_W2 = 0xa6:2;
sbit	FUDR0_W1 = 0xa6:1;
sbit	FUDR0_W0 = 0xa6:0;
sfr	UPID = 0xab;
sbit	FCRC_ERR = 0xab:4;
sbit	FPKT_ERR = 0xab:3;
sbit	FUBDE = 0xab:2;
sbit	FDDP = 0xab:1;
sbit	FDDN = 0xab:0;
sfr	UTOGGLE = 0xac;
sbit	FEP2_DATA01 = 0xac:1;
sbit	FEP1_DATA01 = 0xac:0;
sfr	IHRCU = 0xb0;
sbit	FEP0_IN_STALL = 0xb0:0;
sfr	IHRCL = 0xb1;
sbit	FEP0_OUT_STALL = 0xb1:0;
sfr	P0M = 0xb8;
sbit	FP06M = 0xb8:6;
sbit	FP05M = 0xb8:5;
sbit	FP04M = 0xb8:4;
sbit	FP03M = 0xb8:3;
sbit	FP02M = 0xb8:2;
sbit	FP01M = 0xb8:1;
sbit	FP00M = 0xb8:0;
sfr	PEDGE = 0xbf;
sbit	FP00G1 = 0xbf:1;
sbit	FP00G0 = 0xbf:0;
sfr	P1M = 0xc1;
sbit	FP16M = 0xc1:6;
sbit	FP15M = 0xc1:5;
sbit	FP14M = 0xc1:4;
sbit	FP13M = 0xc1:3;
sbit	FP12M = 0xc1:2;
sbit	FP11M = 0xc1:1;
sbit	FP10M = 0xc1:0;
sfr	INTRQ = 0xc8;
sbit	FUSBIRQ = 0xc8:6;
sbit	FT0IRQ = 0xc8:4;
sbit	FWAKEIRQ = 0xc8:2;
sbit	FP00IRQ = 0xc8:0;
sfr	INTEN = 0xc9;
sbit	FUSBIEN = 0xc9:6;
sbit	FT0IEN = 0xc9:4;
sbit	FWAKEIEN = 0xc9:2;
sbit	FP00IEN = 0xc9:0;
sfr	OSCM = 0xca;
sbit	FCPUM1 = 0xca:4;
sbit	FCPUM0 = 0xca:3;
sbit	FCLKMD = 0xca:2;
sbit	FSTPHX = 0xca:1;
sfr	WDTR = 0xcc;
sfr	PCL = 0xce;
sfr	PCH = 0xcf;
sbit	FPC12 = 0xcf:4;
sbit	FPC11 = 0xcf:3;
sbit	FPC10 = 0xcf:2;
sbit	FPC9 = 0xcf:1;
sbit	FPC8 = 0xcf:0;
sfr	P0 = 0xd0;
sbit	FP06 = 0xd0:6;
sbit	FP05 = 0xd0:5;
sbit	FP04 = 0xd0:4;
sbit	FP03 = 0xd0:3;
sbit	FP02 = 0xd0:2;
sbit	FP01 = 0xd0:1;
sbit	FP00 = 0xd0:0;
sfr	P1 = 0xd1;
sbit	FP17 = 0xd1:7;
sbit	FP16 = 0xd1:6;
sbit	FP15 = 0xd1:5;
sbit	FP14 = 0xd1:4;
sbit	FP13 = 0xd1:3;
sbit	FP12 = 0xd1:2;
sbit	FP11 = 0xd1:1;
sbit	FP10 = 0xd1:0;
sfr	T0M = 0xd8;
sbit	FT0ENB = 0xd8:7;
sbit	FT0RATE2 = 0xd8:6;
sbit	FT0RATE1 = 0xd8:5;
sbit	FT0RATE0 = 0xd8:4;
sfr	T0C = 0xd9;
sfr	STKP = 0xdf;
sbit	FGIE = 0xdf:7;
sbit	FSTKPB2 = 0xdf:2;
sbit	FSTKPB1 = 0xdf:1;
sbit	FSTKPB0 = 0xdf:0;
sfr	P0UR = 0xe0;
sbit	FP06R = 0xe0:6;
sbit	FP05R = 0xe0:5;
sbit	FP04R = 0xe0:4;
sbit	FP03R = 0xe0:3;
sbit	FP02R = 0xe0:2;
sbit	FP01R = 0xe0:1;
sbit	FP00R = 0xe0:0;
sfr	P1UR = 0xe1;
sbit	FP16R = 0xe1:6;
sbit	FP15R = 0xe1:5;
sbit	FP14R = 0xe1:4;
sbit	FP13R = 0xe1:3;
sbit	FP12R = 0xe1:2;
sbit	FP11R = 0xe1:1;
sbit	FP10R = 0xe1:0;
sfr	_YZ = 0xe7;
sfr	STK7L = 0xf0;
sfr	STK7H = 0xf1;
sbit	FS7PC12 = 0xf1:4;
sbit	FS7PC11 = 0xf1:3;
sbit	FS7PC10 = 0xf1:2;
sbit	FS7PC9 = 0xf1:1;
sbit	FS7PC8 = 0xf1:0;
sfr	STK6L = 0xf2;
sfr	STK6H = 0xf3;
sbit	FS6PC12 = 0xf3:4;
sbit	FS6PC11 = 0xf3:3;
sbit	FS6PC10 = 0xf3:2;
sbit	FS6PC9 = 0xf3:1;
sbit	FS6PC8 = 0xf3:0;
sfr	STK5L = 0xf4;
sfr	STK5H = 0xf5;
sbit	FS5PC12 = 0xf5:4;
sbit	FS5PC11 = 0xf5:3;
sbit	FS5PC10 = 0xf5:2;
sbit	FS5PC9 = 0xf5:1;
sbit	FS5PC8 = 0xf5:0;
sfr	STK4L = 0xf6;
sfr	STK4H = 0xf7;
sbit	FS4PC12 = 0xf7:4;
sbit	FS4PC11 = 0xf7:3;
sbit	FS4PC10 = 0xf7:2;
sbit	FS4PC9 = 0xf7:1;
sbit	FS4PC8 = 0xf7:0;
sfr	STK3L = 0xf8;
sfr	STK3H = 0xf9;
sbit	FS3PC12 = 0xf9:4;
sbit	FS3PC11 = 0xf9:3;
sbit	FS3PC10 = 0xf9:2;
sbit	FS3PC9 = 0xf9:1;
sbit	FS3PC8 = 0xf9:0;
sfr	STK2L = 0xfa;
sfr	STK2H = 0xfb;
sbit	FS2PC12 = 0xfb:4;
sbit	FS2PC11 = 0xfb:3;
sbit	FS2PC10 = 0xfb:2;
sbit	FS2PC9 = 0xfb:1;
sbit	FS2PC8 = 0xfb:0;
sfr	STK1L = 0xfc;
sfr	STK1H = 0xfd;
sbit	FS1PC12 = 0xfd:4;
sbit	FS1PC11 = 0xfd:3;
sbit	FS1PC10 = 0xfd:2;
sbit	FS1PC9 = 0xfd:1;
sbit	FS1PC8 = 0xfd:0;
sfr	STK0L = 0xfe;
sfr	STK0H = 0xff;
sbit	FS0PC12 = 0xff:4;
sbit	FS0PC11 = 0xff:3;
sbit	FS0PC10 = 0xff:2;
sbit	FS0PC9 = 0xff:1;
sbit	FS0PC8 = 0xff:0;
#define SLEEPMODE __asm{SleepMode}
#define GREENMODE __asm{GreenMode}
#define SLOWMODE __asm{SlowMode}
#define SLOW2NORMAL __asm{Slow2Normal}
#endif
