;FM8PE531A General Head Ver:1.00,build:0 credit:0 lastedit:20160503
;Header Author:hu_cy; hu_cy@feeling-tech.com.tw
;CHIP Version:N/A(General)
;---------------HEAD Credit History-------------------------------------------
;2016/05/03	Release
;---------------Common define Segment-----------------------------------------
A		EQU	0x0
R		EQU	0x1
;---------------Operation Registers Maps--------------------------------------
INDF		REG	0x00
PCL		REG	0x02
;-------------------------------
STATUS		REG	0x03
C_B		EQU	0x0
DC_B		EQU	0x1
Z_B		EQU	0x2
PD_B		EQU	0x3
TO_B		EQU	0x4
PG0_B		EQU	0x5
PG1_B		EQU	0x6
RST_B		EQU	0x7
;-------------------------------
FSR		REG	0x04
RP0_B		EQU	0x6
RP1_B		EQU	0x7
;-------------------------------
IOSTA		REG	0x05
IOSTA0_B	EQU	0x0
IOSTA1_B	EQU	0x1
IOSTA2_B	EQU	0x2
IOSTA3_B	EQU	0x3
IOSTA4_B	EQU	0x4
IOSTA5_B	EQU	0x5
;-------------------------------
PORTA		REG	0x06
IOA0_B		EQU	0x0
IOA1_B		EQU	0x1
IOA2_B		EQU	0x2
IOA3_B		EQU	0x3
IOA4_B		EQU	0x4
IOA5_B		EQU	0x5
;-------------------------------
IOSTB		REG	0x07
IOSTB0_B	EQU	0x0
IOSTB1_B	EQU	0x1
IOSTB2_B	EQU	0x2
IOSTB3_B	EQU	0x3
IOSTB4_B	EQU	0x4
IOSTB5_B	EQU	0x5
IOSTB6_B	EQU	0x6
IOSTB7_B	EQU	0x7
;-------------------------------
PORTB		REG	0x08
IOB0_B		EQU	0x0
IOB1_B		EQU	0x1
IOB2_B		EQU	0x2
IOB3_B		EQU	0x3
IOB4_B		EQU	0x4
IOB5_B		EQU	0x5
IOB6_B		EQU	0x6
IOB7_B		EQU	0x7
;-------------------------------
T1CON		REG	0x09
T1EN_B		EQU	0x0
T1CS_B		EQU	0x1
T1PS0_B		EQU	0x3
T1PS1_B		EQU	0x4
;-------------------------------
TMR1LB		REG	0x0A
TMR1HB		REG	0x0B
;-------------------------------
OSCCON		REG	0x0C
IRCF0_B		EQU	0x0
IRCF1_B		EQU	0x1
IRCF2_B		EQU	0x2
CPUS_B		EQU	0x3
WDTSEL0_B	EQU	0x4
WDTSEL1_B	EQU	0x5
IRCEN_B		EQU	0x6
WDTEN_B		EQU	0x7
;-------------------------------
LVDTCON		REG	0x0D
LVDSEL0_B	EQU	0x0
LVDSEL1_B	EQU	0x1
LVDSEL2_B	EQU	0x2
INTEDG_B	EQU	0x3
LVREN_B		EQU	0x4
IOB3EN_B	EQU	0x5
RDPORT_B	EQU	0x6
EIS_B		EQU	0x7
;-------------------------------
INTEN		REG	0x0E
T1IE_B		EQU	0x0
RFCIE_B		EQU	0x1
INTIE_B		EQU	0x2
CMPIE_B		EQU	0x3
LVDTIE_B	EQU	0x4
GIE_B		EQU	0x7
;-------------------------------
INTFLAG		REG	0x0F
T1IF_B		EQU	0x0
RFCIF_B		EQU	0x1
INTIF_B		EQU	0x2
CMPIF_B		EQU	0x3
LVDTIF_B	EQU	0x4
;---------------Operation Registers Maps in Bank0,1---------------------------
.SET BANK0
PWMCON		REG	0x10
P0EN_B		EQU	0x0
P1EN_B		EQU	0x1
PWMCS0_B	EQU	0x2
PWMCS1_B	EQU	0x3
PWMCS2_B	EQU	0x4
;-------------------------------
P0DPR		REG	0x11
P1DPR		REG	0x12
;-------------------------------
RFCCON		REG	0x13
RFCS0_B		EQU	0x0
RFCS1_B		EQU	0x1
RFCMOD_B	EQU	0x4
START_B		EQU	0x6
RFCON_B		EQU	0x7
;-------------------------------
RFCDLB		REG	0x14
;-------------------------------
RFCDHB		REG	0x15
RFCOV_B		EQU	0x7		;Note: RFCDx is bit layout, not define
.ENDSET
;---------------Operation Registers Maps in Bank2,3---------------------------
.SET BANK2
AWUCON		REG	0x10
WUA0_B		EQU	0x0
WUA1_B		EQU	0x1
WUA2_B		EQU	0x2
WUA3_B		EQU	0x3
WUA4_B		EQU	0x4
WUA5_B		EQU	0x5
;-------------------------------
APHCON		REG	0x11
PHA0_B		EQU	0x0
PHA1_B		EQU	0x1
PHA2_B		EQU	0x2
PHA3_B		EQU	0x3
PHA4_B		EQU	0x4
PHA5_B		EQU	0x5
;-------------------------------
BWUCON		REG	0x12
WUB0_B		EQU	0x0
WUB1_B		EQU	0x1
WUB2_B		EQU	0x2
WUB3_B		EQU	0x3
WUB4_B		EQU	0x4
WUB5_B		EQU	0x5
WUB6_B		EQU	0x6
WUB7_B		EQU	0x7
;-------------------------------
BPHCON		REG	0x13
PHB0_B		EQU	0x0
PHB1_B		EQU	0x1
PHB2_B		EQU	0x2
PHB4_B		EQU	0x4
PHB5_B		EQU	0x5
PHB6_B		EQU	0x6
PHB7_B		EQU	0x7
;-------------------------------
CMPCON1		REG	0x14
CM0_B		EQU	0x0
CM1_B		EQU	0x1
CM2_B		EQU	0x2
CINS_B		EQU	0x3
CINV_B		EQU	0x4
COUT_B		EQU	0x5
;-------------------------------
CMPCON2		REG	0x15
CVR0_B		EQU	0x0
CVR1_B		EQU	0x1
CVR2_B		EQU	0x2
CVR3_B		EQU	0x3
CVRR_B		EQU	0x4
CVREN_B		EQU	0x5
.ENDSET
