#ifndef __BL2101_H__
#define __BL2101_H__

/*
 * ==========================================================================
 * ---------- Interrupt Number Definition -----------------------------------
 * ==========================================================================
 */
typedef enum IRQn
{
/******  Cortex-M0 Processor Exceptions Numbers **********************************************/
  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                        */
  HardFault_IRQn	          = -13,	/*!< 3 Cortex-M0 Hard Fault Interrupt				 */
  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M0 SV Call Interrupt                  */
  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0 Pend SV Interrupt                  */
  SysTick_IRQn                = -1,     /*!< 15 Cortex-M0 System Tick Interrupt              */
  
/******  Cortex-M0 specific Interrupt Numbers ************************************************/
  UART0_IRQn          = 0,
  UART1_IRQn          = 1,
  UART2_IRQn          = 2,
  TIMER_IRQn          = 3,
  PWM_IRQn            = 4,
  ADC_IRQn            = 5,
  RTC_IRQn            = 6,
  IIC_IRQn            = 7,
  SPI_IRQn            = 8,
  AES_IRQn            = 9,
  WDT_IRQn            = 10,
  GPIOA0_IRQn         = 11,
  GPIOA1_IRQn         = 12,
  GPIOA4_IRQn         = 13,
  GPIOA5_IRQn         = 14,
  GPIOB0_IRQn         = 15,
  GPIOB1_IRQn         = 16,
  GPIOA14_IRQn        = 17,
  GPIOA15_IRQn        = 18,	
  GPIOA_IRQn          = 19,
  GPIOB_IRQn          = 20,
  IRQ21_IRQn          = 21,
  IRQ22_IRQn          = 22,
  IRQ23_IRQn          = 23,
  IRQ24_IRQn          = 24,
  IRQ25_IRQn          = 25,
  IRQ26_IRQn          = 26,
  IRQ27_IRQn          = 27,
  IRQ28_IRQn          = 28,
  IRQ29_IRQn          = 29,
  IRQ30_IRQn          = 30,
  IRQ31_IRQn          = 31,
} IRQn_Type;

/*
 * ==========================================================================
 * ----------- Processor and Core Peripheral Section ------------------------
 * ==========================================================================
 */

/* Configuration of the Cortex-M0 Processor and Core Peripherals */
#define __MPU_PRESENT		    0	   /*!< UART does not provide a MPU present or not	     */
#define __NVIC_PRIO_BITS		2	   /*!< UART Supports 2 Bits for the Priority Levels	 */
#define __Vendor_SysTickConfig  0	   /*!< Set to 1 if different SysTick Config is used	 */

#if   defined ( __CC_ARM )
  #pragma anon_unions
#endif

#include <stdio.h>
#include "core_cm0.h"				   /* Cortex-M0 processor and core peripherals		     */

typedef enum {RESET = 0, SET = 1} FlagStatus, ITStatus;

typedef enum {DISABLE = 0, ENABLE = 1} FunctionalState;

#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))

typedef enum {ERROR = 0, SUCCESS = 1} ErrorStatus;


/******************************************************************************/
/*				Device Specific Peripheral registers structures			 */
/******************************************************************************/

typedef struct {
	__IO uint32_t CLKSEL;				//Clock Select

	__IO uint32_t CLKDIV_EN;			//CLK_DIV时钟源开关

	__IO uint32_t CLKEN;			    //外设Clock Enable

	uint32_t RESERVED1[1];
	
	__IO uint32_t WDTRST_ST;            //看门狗复位状态             
	
	uint32_t RESERVED3[(0x84 - 0x14)/4];
	
	__IO uint32_t XTALCR;					//XTAL Control Register
} SYS_TypeDef;

#define SYS_CLKSEL_SYS_POS		  0		//系统时钟选择	0 HRC  1 CLK_DIVx
#define SYS_CLKSEL_SYS_MSK		  (0x01 << SYS_CLKSEL_SYS_POS)

#define SYS_CLKSEL_DIV_POS		  1		//选择CLK_DIVx  0 CLK_DIV1   1 CLK_DIV2   2 CLK_DIV4   3 CLK_DIV8
#define SYS_CLKSEL_DIV_MSK		  (0x03 << SYS_CLKSEL_DIV_POS)

#define SYS_CLKSEL_SRC_POS		  3		//选择SRC  0 HRC   1 LRC   2 XTAL   3 RESERVED
#define SYS_CLKSEL_SRC_MSK		  (0x03 << SYS_CLKSEL_SRC_POS)

#define SYS_CLKSEL_ADC_POS		  6		//ADC采样时钟选择  0 1分频   1 2分频   2 4分频   3 8分频
#define SYS_CLKSEL_ADC_MSK		  (0x03 << SYS_CLKSEL_ADC_POS)

#define SYS_CLKSEL_WDT_POS		  8		//WDT时钟选择	0 LRC	1 SYS
#define SYS_CLKSEL_WDT_MSK		  (0x01 << SYS_CLKSEL_WDT_POS)


#define SYS_CLKDIV_EN_DIV_POS	  0		//分频时钟选择	0 使能分频时钟输出  1 禁止分频时钟输出	
#define SYS_CLKDIV_EN_DIV_MSK     (0x01 << SYS_CLKDIV_EN_DIV_POS)


#define SYS_CLKEN_GPIOA_POS		  0		//GPIOA时钟门控   
#define SYS_CLKEN_GPIOA_MSK		  (0x01 << SYS_CLKEN_GPIOA_POS)

#define SYS_CLKEN_GPIOB_POS		  1		//GPIOB时钟门控   
#define SYS_CLKEN_GPIOB_MSK		  (0x01 << SYS_CLKEN_GPIOB_POS)

#define SYS_CLKEN_IIC_POS		  4		//IIC时钟门控   
#define SYS_CLKEN_IIC_MSK		  (0x01 << SYS_CLKEN_IIC_POS)

#define SYS_CLKEN_WDT_POS		  6		//WDT时钟门控   
#define SYS_CLKEN_WDT_MSK		  (0x01 << SYS_CLKEN_WDT_POS)

#define SYS_CLKEN_RTC_POS		  7		//RTC时钟门控   
#define SYS_CLKEN_RTC_MSK		  (0x01 << SYS_CLKEN_RTC_POS)

#define SYS_CLKEN_TIMER_POS		  8		//TIMER时钟门控   
#define SYS_CLKEN_TIMER_MSK	      (0x01 << SYS_CLKEN_TIMER_POS)

#define SYS_CLKEN_PWM_POS		  9		//PWM时钟门控   
#define SYS_CLKEN_PWM_MSK		  (0x01 << SYS_CLKEN_PWM_POS)

#define SYS_CLKEN_SPI_POS		  10    //SPI时钟门控   
#define SYS_CLKEN_SPI_MSK		  (0x01 << SYS_CLKEN_SPI_POS)

#define SYS_CLKEN_UART0_POS		  14    //UART时钟门控   
#define SYS_CLKEN_UART0_MSK		  (0x01 << SYS_CLKEN_UART0_POS)

#define SYS_CLKEN_UART1_POS		  15    //UART1时钟门控   
#define SYS_CLKEN_UART1_MSK		  (0x01 << SYS_CLKEN_UART1_POS)

#define SYS_CLKEN_UART2_POS		  16    //UART2时钟门控   
#define SYS_CLKEN_UART2_MSK		  (0x01 << SYS_CLKEN_UART2_POS)

#define SYS_CLKEN_AES_POS		   20   //AES时钟门控   
#define SYS_CLKEN_AES_MSK		  (0x01 << SYS_CLKEN_AES_POS)

#define SYS_CLKEN_ADC_POS		   21   //ADC时钟门控   
#define SYS_CLKEN_ADC_MSK		  (0x01 << SYS_CLKEN_ADC_POS)


#define SYS_WDTRST_ST_POS		   0	//看门狗复位状态
#define SYS_WDTRST_ST_MSK		  (0x01 << SYS_WDTRST_ST_POS)


#define SYS_XTAL_EN_POS		       0	//XTAL使能
#define SYS_XTAL_EN_MSK		       (0x01 << SYS_XTAL_EN_POS)


typedef struct {
	__IO uint32_t PORTA_SEL;                //功能选择
	
	__IO uint32_t PORTB_SEL;
	
	uint32_t RESERVED1[(0x100 - 0x08)/4];
	
	__IO uint32_t PORTA_INEN;               //输入使能
	
	__IO uint32_t PORTB_INEN; 

	uint32_t RESERVED2[(0x200 - 0x108)/4];
	
	__IO uint32_t PORTA_PU_IN;              //上拉使能
		 
    __IO uint32_t PORTB_PU_IN;  
	
	uint32_t RESERVED3[(0x300 - 0x208)/4];
	
    __IO uint32_t PORTA_PD_IN;              //下拉使能
  
	__IO uint32_t PORTB_PD_IN;
	
    uint32_t RESERVED4[(0x400 - 0x308)/4];     
			 
	__IO uint32_t PORTA_OD_OUT;              //开漏使能
    
    __IO uint32_t PORTB_OD_OUT; 
 
    uint32_t RESERVED5[(0x500 - 0x408)/4]; 
	
	__IO uint32_t PORTA_WAKEUP;             //唤醒使能
    
    __IO uint32_t PORTB_WAKEUP; 

    uint32_t RESERVED6[(0x700 - 0x508)/4]; 
	
	__IO uint32_t PORT_CFG;                 //端口配置
} PORT_TypeDef;


#define PORT_CFG_A0_7_DS_POS		    0		//A0_7驱动能力选择  00 5ma  01 14ma  10 22ma  11 30ma 
#define PORT_CFG_A0_7_DS_MSK		    (0x03 << PORT_CFG_A0_7_DS_POS)

#define PORT_CFG_A8_15_DS_POS		    2		//A8_15驱动能力选择  00 5ma  01 14ma  10 22ma  11 30ma 
#define PORT_CFG_A8_15_DS_MSK		    (0x03 << PORT_CFG_A8_15_DS_POS)

#define PORT_CFG_B0_7_DS_POS		    4		//B0_7驱动能力选择  00 5ma  01 14ma  10 22ma  11 30ma 
#define PORT_CFG_B0_7_DS_MSK		    (0x03 << PORT_CFG_B0_7_DS_POS)

#define PORT_CFG_PUR_POS		        8		//上拉电阻选择  00 保留  01  150K   10 40K    11  32K  
#define PORT_CFG_PUR_MSK		        (0x03 << PORT_CFG_PUR_POS)

#define PORT_CFG_HYS_POS		        10		//输入迟滞等级选择  0  低输入 >0.7VDD  <0.3VDD   1 高输入  >0.85VDD <0.15VDD 
#define PORT_CFG_HYS_MSK		        (0x01 << PORT_CFG_HYS_POS)

#define PORT_CFG_WKRF_POS		        11		//唤醒功能沿选择  0  下降沿  1上升沿
#define PORT_CFG_WKRF_MSK		        (0x01 << PORT_CFG_WKRF_POS)


typedef struct {
	__IO uint32_t DATA;                 //数据寄存器

	__IO uint32_t DIR;					//0 输入	1 输出

	__IO uint32_t INTLVLTRG;			//Interrupt Level Trigger  1 电平触发中断	0 边沿触发中断

	__IO uint32_t INTBE;			    //Both Edge，当INTLVLTRG设为边沿触发中断时，此位置1表示上升沿和下降沿都触发中断，置0时触发边沿由INTRISEEN选择

	__IO uint32_t INTRISEEN;			//Interrupt Rise Edge Enable   1 上升沿/高电平触发中断	0 下降沿/低电平触发中断

	__IO uint32_t INTEN;			    //1 中断使能	0 中断禁止

	__IO uint32_t INTRAWSTAT;			//中断检测单元是否检测到了触发中断的条件 1 检测到了中断触发条件	0 没有检测到中断触发条件

	__IO uint32_t INTSTAT;				//INTSTAT.PIN0 = INTRAWSTAT.PIN0 & INTEN.PIN0

	__IO uint32_t INTCLR;			    //写1清除中断标志，只对边沿触发中断有用

} GPIO_TypeDef;



typedef struct {
	__IO uint32_t EN;             //定时器使能
	
	__IO uint32_t DIV;            //定时器分频值
	
	__IO uint32_t CTR;            //定时器级联控制寄存器
	
	uint32_t RESERVED1[1];
	
	__IO uint32_t IE;             //中断使能寄存器
		
	__IO uint32_t STAT;           //状态寄存器
	
	uint32_t RESERVED2[(0x80 - 0x18)/4];
	
	__IO uint32_t LOAD;						//定时器加载值，使能后定时器从0开始计数到该加载值后产生中断状态
	
	__IO uint32_t CNT;                      //当前计数值
	
} TIMER_TypeDef;


#define TIMER_LOW16BIT_EN_POS         0        //低16位定时器使能寄存器    级联32位定时器时由该位控制
#define TIMER_LOW16BIT_EN_MSK         (0x01 << TIMER_LOW16BIT_EN_POS)

#define TIMER_HIGH16BIT_EN_POS        1        //高16位定时器使能寄存器    级联32位定时器时该位无效
#define TIMER_HIGH16BIT_EN_MSK        (0x01 << TIMER_HIGH16BIT_EN_POS)

#define TIMER_DIV_POS                 0        //定时器分频寄存器  0 1分频   1  2分频    FF 256分频
#define TIMER_DIV_MSK                 (0xFF << TIMER_DIV_POS)  

#define TIMER_CTR_POS                 0        //级联控制寄存器    0表示独立   1表示级联
#define TIMER_CTR_MSK                 (0x01 << TIMER_CTR_POS)

#define TIMER_IE_LOW16BIT_POS         0        //低16位中断使能寄存器    级联模式下该位无效   
#define TIMER_IE_LOW16BIT_MSK         (0x01 << TIMER_IE_LOW16BIT_POS)

#define TIMER_IE_HIGH16BIT_POS        1        //高16位中断使能寄存器    级联模式下该位无效   
#define TIMER_IE_HIGH16BIT_MSK        (0x01 << TIMER_IE_HIGH16BIT_POS)

#define TIMER_IE_32BIT_POS            2        //32位中断使能寄存器    只有级联模式下该位才有效 
#define TIMER_IE_32BIT_MSK            (0x01 << TIMER_IE_32BIT_POS)

#define TIMER_STAT_LOW16BIT_POS       0        //低16位状态寄存器    级联模式下该位无效   
#define TIMER_STAT_LOW16BIT_MSK       (0x01 << TIMER_STAT_LOW16BIT_POS)

#define TIMER_STAT_HIGH16BIT_POS      1        //高16位状态寄存器    级联模式下该位无效   
#define TIMER_STAT_HIGH16BIT_MSK      (0x01 << TIMER_STAT_HIGH16BIT_POS)

#define TIMER_STAT_32BIT_POS          2        //32位状态寄存器    只有级联模式下该位才有效 
#define TIMER_STAT_32BIT_MSK          (0x01 << TIMER_STAT_32BIT_POS)

#define TIMER_LOAD_LOW16BIT_POS       0        //低16位定时器目标配置寄存器
#define TIMER_LOAD_LOW16BIT_MSK       (0xFFFF << TIMER_LOAD_LOW16BIT_POS)

#define TIMER_LOAD_HIGH16BIT_POS      16       //高16位定时器目标配置寄存器
#define TIMER_LOAD_HIGH16BIT_MSK      (0xFFFF << TIMER_LOAD_HIGH16BIT_POS)

#define TIMER_CNT_LOW16BIT_POS        0        //低16位定时器目标配置寄存器
#define TIMER_CNT_LOW16BIT_MSK        (0xFFFF << TIMER_CNT_LOW16BIT_POS)

#define TIMER_CNT_HIGH16BIT_POS       16       //高16位定时器目标配置寄存器
#define TIMER_CNT_HIGH16BIT_MSK       (0xFFFF << TIMER_CNT_HIGH16BIT_POS)

typedef struct {
	__IO uint32_t EN;                     //PWM使能寄存器
											
	__IO uint32_t DIV;                    //PWM分频寄存器
	
	__IO uint32_t INV;                    //PWM翻转寄存器
	
	uint32_t RESERVED1[1];
	
	__IO uint32_t IE;                     //PWM中断使能寄存器
	
	__IO uint32_t IF;                     //PWM中断状态寄存器
} PWMG_TypeDef;

typedef struct {
	__IO uint32_t PERIOD;                 //PWM周期配置寄存器
											
	__IO uint32_t HIGH;                   //PWM高电平配置寄存器
} PWM_TypeDef;


#define PWMG_PWM0_EN_POS           0   //PWM0使能寄存器
#define PWMG_PWM0_EN_MSK           (0x01 << PWMG_PWM0_EN_POS)

#define PWMG_PWM1_EN_POS           1   //PWM1使能寄存器
#define PWMG_PWM1_EN_MSK           (0x01 << PWMG_PWM1_EN_POS)

#define PWMG_PWM2_EN_POS           2   //PWM2使能寄存器
#define PWMG_PWM2_EN_MSK           (0x01 << PWMG_PWM2_EN_POS)

#define PWMG_PWM3_EN_POS           3   //PWM3使能寄存器
#define PWMG_PWM3_EN_MSK           (0x01 << PWMG_PWM3_EN_POS)

#define PWMG_PWM4_EN_POS           4   //PWM4使能寄存器
#define PWMG_PWM4_EN_MSK           (0x01 << PWMG_PWM4_EN_POS)

#define PWMG_DIV_POS               0   //PWM时钟分频寄存器
#define PWMG_DIV_MSK               (0x07 << PWMG_DIV_POS)

#define PWMG_PWM0_INV_POS          0   //PWM0翻转寄存器
#define PWMG_PWM0_INV_MSK          (0x01 << PWMG_PWM0_INV_POS)

#define PWMG_PWM1_INV_POS          1   //PWM1翻转寄存器
#define PWMG_PWM1_INV_MSK          (0x01 << PWMG_PWM1_INV_POS)

#define PWMG_PWM2_INV_POS          2   //PWM2翻转寄存器
#define PWMG_PWM2_INV_MSK          (0x01 << PWMG_PWM2_INV_POS)

#define PWMG_PWM3_INV_POS          3  //PWM3翻转寄存器
#define PWMG_PWM3_INV_MSK          (0x01 << PWMG_PWM3_INV_POS)

#define PWMG_PWM4_INV_POS          4   //PWM4翻转寄存器
#define PWMG_PWM4_INV_MSK          (0x01 << PWMG_PWM4_INV_POS)

#define PWMG_PWM0_HEND_IE_POS      0   //PWM0高电平结束中断使能
#define PWMG_PWM0_HEND_IE_MSK      (0x01 << PWMG_PWM0_HEND_IE_POS)

#define PWMG_PWM0_OVF_IE_POS       1   //PWM0周期溢出中断使能
#define PWMG_PWM0_OVF_IE_MSK       (0x01 << PWMG_PWM0_OVF_IE_POS)

#define PWMG_PWM1_HEND_IE_POS      4   //PWM1高电平结束中断使能
#define PWMG_PWM1_HEND_IE_MSK      (0x01 << PWMG_PWM1_HEND_IE_POS)

#define PWMG_PWM1_OVF_IE_POS       5   //PWM1周期溢出中断使能
#define PWMG_PWM1_OVF_IE_MSK       (0x01 << PWMG_PWM1_OVF_IE_POS)

#define PWMG_PWM2_HEND_IE_POS      8   //PWM2高电平结束中断使能
#define PWMG_PWM2_HEND_IE_MSK      (0x01 << PWMG_PWM2_HEND_IE_POS)

#define PWMG_PWM2_OVF_IE_POS       9   //PWM2周期溢出中断使能
#define PWMG_PWM2_OVF_IE_MSK       (0x01 << PWMG_PWM2_OVF_IE_POS)

#define PWMG_PWM3_HEND_IE_POS      12  //PWM3高电平结束中断使能
#define PWMG_PWM3_HEND_IE_MSK      (0x01 << PWMG_PWM3_HEND_IE_POS)

#define PWMG_PWM3_OVF_IE_POS       13  //PWM3周期溢出中断使能
#define PWMG_PWM3_OVF_IE_MSK       (0x01 << PWMG_PWM3_OVF_IE_POS)

#define PWMG_PWM4_HEND_IE_POS      16  //PWM4高电平结束中断使能
#define PWMG_PWM4_HEND_IE_MSK      (0x01 << PWMG_PWM4_HEND_IE_POS)

#define PWMG_PWM4_OVF_IE_POS       17  //PWM4周期溢出中断使能
#define PWMG_PWM4_OVF_IE_MSK       (0x01 << PWMG_PWM4_OVF_IE_POS)


#define PWMG_PWM0_HEND_IF_POS      0   //PWM0高电平结束中断状态
#define PWMG_PWM0_HEND_IF_MSK      (0x01 << PWMG_PWM0_HEND_IF_POS)

#define PWMG_PWM0_OVF_IF_POS       1   //PWM0周期溢出中断状态
#define PWMG_PWM0_OVF_IF_MSK       (0x01 << PWMG_PWM0_OVF_IF_POS)

#define PWMG_PWM1_HEND_IF_POS      4   //PWM1高电平结束中断状态
#define PWMG_PWM1_HEND_IF_MSK      (0x01 << PWMG_PWM1_HEND_IF_POS)

#define PWMG_PWM1_OVF_IF_POS       5   //PWM1周期溢出中断状态
#define PWMG_PWM1_OVF_IF_MSK       (0x01 << PWMG_PWM1_OVF_IF_POS)

#define PWMG_PWM2_HEND_IF_POS      8   //PWM2高电平结束中断状态
#define PWMG_PWM2_HEND_IF_MSK      (0x01 << PWMG_PWM2_HEND_IF_POS)

#define PWMG_PWM2_OVF_IF_POS       9   //PWM2周期溢出中断状态
#define PWMG_PWM2_OVF_IF_MSK       (0x01 << PWMG_PWM2_OVF_IF_POS)

#define PWMG_PWM3_HEND_IF_POS      12  //PWM3高电平结束中断状态
#define PWMG_PWM3_HEND_IF_MSK      (0x01 << PWMG_PWM3_HEND_IF_POS)

#define PWMG_PWM3_OVF_IF_POS       13  //PWM3周期溢出中断状态
#define PWMG_PWM3_OVF_IF_MSK       (0x01 << PWMG_PWM3_OVF_IF_POS)

#define PWMG_PWM4_HEND_IF_POS      16  //PWM4高电平结束中断状态
#define PWMG_PWM4_HEND_IF_MSK      (0x01 << PWMG_PWM4_HEND_IF_POS)

#define PWMG_PWM4_OVF_IF_POS       17  //PWM4周期溢出中断状态
#define PWMG_PWM4_OVF_IF_MSK       (0x01 << PWMG_PWM4_OVF_IF_POS)

#define PWM_PERIOD_POS             0  //PWM输出周期配置寄存器
#define PWM_PERIOD_MSK             (0xFFF << PWM_PERIOD_POS)

#define PWM_HIGH_POS               0  //PWM输出高电平配置寄存器
#define PWM_HIGH_MSK               (0xFFF << PWM_HIGH_POS)


typedef struct {
    __IO uint32_t EN;               //[0] 1 RTC使能
    
    __IO uint32_t ALARM;            //闹钟设置寄存器
    
    __IO uint32_t SECOND;           //秒设置寄存器
    
    __IO uint32_t TIME;             //时间计数器
    
    __IO uint32_t IE;               //中断使能寄存器
	
	__IO uint32_t IF;               //中断状态寄存器
 
} RTC_TypeDef;


#define RTC_SECOND_IE_POS     0   //RTC秒中断使能
#define RTC_SECOND_IE_MSK     (0x01 << RTC_SECOND_IE_POS)

#define RTC_ALARM_IE_POS      1   //RTC闹钟中断使能
#define RTC_ALARM_IE_MSK      (0x01 << RTC_ALARM_IE_POS)

#define RTC_OVF_IE_POS        2   //RTC溢出中断使能
#define RTC_OVF_IE_MSK        (0x01 << RTC_OVF_IE_POS)

#define RTC_SECOND_IF_POS     0   //RTC秒中断状态
#define RTC_SECOND_IF_MSK     (0x01 << RTC_SECOND_IF_POS)

#define RTC_ALARM_IF_POS      1   //RTC闹钟中断状态
#define RTC_ALARM_IF_MSK      (0x01 << RTC_ALARM_IF_POS)

#define RTC_OVF_IF_POS        2   //RTC溢出中断状态
#define RTC_OVF_IF_MSK        (0x01 << RTC_OVF_IF_POS)



typedef struct {
	__IO uint32_t LOAD;					    //WDT计数器初始值
	
	__IO uint32_t VALUE;					//WDT当前计数值
	
	__IO uint32_t CTRL;                     //WDT控制寄存器
	
	__IO uint32_t IF;						//[0] 中断标志，写0清除 
	
	__IO uint32_t FEED;                     //喂狗寄存器  写入0x55即可喂狗
	
} WDT_TypeDef;


#define WDT_CTRL_EN_POS      0   //WDT启动使能
#define WDT_CTRL_EN_MSK      (0x01 << WDT_CTRL_EN_POS)

#define WDT_CTRL_RSTEN_POS   1   //WDT复位输出使能
#define WDT_CTRL_RSTEN_MSK   (0x01 << WDT_CTRL_RSTEN_POS)


typedef struct {
	__IO uint32_t CTRL;       //控制寄存器

	__IO uint32_t WDATA;      //写数据寄存器

	__IO uint32_t RDATA;      //读数据寄存器

	uint32_t RESERVED1[1];
	
	__IO uint32_t IE;         //中断使能

	__IO uint32_t IF;         //中断状态
	
} SPI_TypeDef;


#define SPI_CTRL_CLKDIV_POS     0           //Clock Divider, SPI工作时钟 = SYS_Freq/pow(2, CLKDIV+2)
#define SPI_CTRL_CLKDIV_MSK     (0x07 << SPI_CTRL_CLKDIV_POS)

#define SPI_CTRL_EN_POS         3           //SPI系统使能
#define SPI_CTRL_EN_MSK         (0x01 << SPI_CTRL_EN_POS)

#define SPI_CTRL_CPHA_POS		4		    //0 在SCLK的第一个跳变沿采样数据	1 在SCLK的第二个跳变沿采样数据
#define SPI_CTRL_CPHA_MSK		(0x01 << SPI_CTRL_CPHA_POS)

#define SPI_CTRL_CPOL_POS		5		    //0 空闲状态下SCLK为低电平		  1 空闲状态下SCLK为高电平
#define SPI_CTRL_CPOL_MSK		(0x01 << SPI_CTRL_CPOL_POS)

#define SPI_CTRL_MSTR_POS		6		    //Master, 1 主模式	0 从模式
#define SPI_CTRL_MSTR_MSK		(0x01 << SPI_CTRL_MSTR_POS)

#define SPI_CTRL_LSBF_POS		7		    //数据传输顺序选择  0 MSB Fisrt  1 LSB Fisrt
#define SPI_CTRL_LSBF_MSK		(0x01 << SPI_CTRL_LSBF_POS)

#define SPI_CTRL_DATAHOLD_POS   8           //从模式下CPHA为1时，数据保持时间配置寄存器
#define SPI_CTRL_DATAHOLD_MSK   (0x0F << SPI_CTRL_DATAHOLD_POS)

#define SPI_CTRL_MST_SSN_POS    12          //主机模式下，SSN输出   默认输出高电平
#define SPI_CTRL_MST_SSN_MSK    (0x01 << SPI_CTRL_MST_SSN_POS)

#define SPI_SPIF_IE_POS         1           //传输结束中断使能
#define SPI_SPIF_IE_MSK         (0x01 << SPI_SPIF_IE_POS)

#define SPI_WDFL_IE_POS         2           //写数据冲突中断使能
#define SPI_WDFL_IE_MSK         (0x01 << SPI_WDFL_IE_POS)

#define SPI_SPIF_IF_POS         1           //传输结束中断状态
#define SPI_SPIF_IF_MSK         (0x01 << SPI_SPIF_IF_POS)

#define SPI_WDFL_IF_POS         2           //写数据冲突中断状态
#define SPI_WDFL_IF_MSK         (0x01 << SPI_WDFL_IF_POS)


typedef struct {
	__IO uint32_t CR;              //控制寄存器
            
	__IO uint32_t SR;              //状态寄存器

	__IO uint32_t DINR;            //输入数据寄存器

	__IO uint32_t DOUTR;           //输出数据寄存器

	__IO uint32_t KEYR0;           //密钥寄存器0
	
	__IO uint32_t KEYR1;           //密钥寄存器1
	
	__IO uint32_t KEYR2;           //密钥寄存器2
	
	__IO uint32_t KEYR3;           //密钥寄存器3
	
	__IO uint32_t IVR0;            //加密起始点寄存器0
	
	__IO uint32_t IVR1;            //加密起始点寄存器1
	
	__IO uint32_t IVR2;            //加密起始点寄存器2
	
	__IO uint32_t IVR3;            //加密起始点寄存器3
	
} AES128_TypeDef;

#define AES128_CR_EN_POS               0          //AES128使能信号
#define AES128_CR_EN_MSK               (0x01 << AES128_CR_EN_POS)

#define AES128_CR_DATATYPE_POS         1          //AES128数据类型选择
#define AES128_CR_DATATYPE_MSK         (0x03 << AES128_CR_DATATYPE_POS)

#define AES128_CR_MODE_POS             3          //AES128模式选择
#define AES128_CR_MODE_MSK             (0x03 << AES128_CR_MODE_POS)

#define AES128_CR_CHMODE_POS           5          //AES128链接模式选择
#define AES128_CR_CHMODE_MSK           (0x03 << AES128_CR_CHMODE_POS)

#define AES128_CR_CCFC_POS             7          //AES128计算完成标志清除
#define AES128_CR_CCFC_MSK             (0x01 << AES128_CR_CCFC_POS)

#define AES128_CR_ERRC_POS             8          //AES128错误标志清除
#define AES128_CR_ERRC_MSK             (0x01 << AES128_CR_ERRC_POS)

#define AES128_CR_CCFIE_POS            9          //AES128计算完成中断使能
#define AES128_CR_CCFIE_MSK            (0x01 << AES128_CR_CCFIE_POS)

#define AES128_CR_ERRIE_POS            10         //AES128错误中断使能
#define AES128_CR_ERRIE_MSK            (0x01 << AES128_CR_ERRIE_POS)

#define AES128_SR_CCF_POS              0          //AES128计算完成标志
#define AES128_SR_CCF_MSK              (0x01 << AES128_SR_CCF_POS)

#define AES128_SR_RDERR_POS            1          //AES128读取错误标志
#define AES128_SR_RDERR_MSK            (0x01 << AES128_SR_RDERR_POS)

#define AES128_SR_WRERR_POS            2          //AES128写入错误标志
#define AES128_SR_WRERR_MSK            (0x01 << AES128_SR_WRERR_POS)


typedef struct {
	__IO uint32_t CFG;                //控制寄存器
	__IO uint32_t PROGDATA;           //编程数据寄存器
	__IO uint32_t ADDR;               //地址寄存器
	__IO uint32_t PROGEN;             //编程使能寄存器
	__IO uint32_t RDATA;              //读数据寄存器
	__IO uint32_t RDEN;               //读使能寄存器
	
	__IO uint32_t PROG_UNLOCK;        //解锁寄存器
	
} OTP_TypeDef;

#define OTP_CFG_MD_POS           0             //读速率模式选择
#define OTP_CFG_MD_MASK          (0x0F<<OTP_CFG_MD_POS)

#define OTP_CFG_TPW_POS          4             //TPW时间寄存器
#define OTP_CFG_TPW_MASK         (0x7FF<<OTP_CFG_TPW_POS)

#define OTP_CFG_TCPS_POS         16            //TPCS时间寄存器
#define OTP_CFG_TCPS_MASK        (0xFF<<OTP_CFG_TCPS_POS)

#define OTP_CFG_SDY_POS          31            //进入STANDBY状态寄存器
#define OTP_CFG_SDY_MASK         (0x01<<OTP_CFG_SDY_POS)

#define OTP_PROGEN_EN_POS        0             //编程使能寄存器
#define OTP_PROGEN_EN_MASK       (0x01<<OTP_PROGEN_EN_POS)

#define OTP_PROGEN_ST_POS        1             //编程状态寄存器
#define OTP_PROGEN_ST_MASK       (0x01<<OTP_PROGEN_ST_POS)

#define OTP_PROGEN_FAIL_POS      2             //编程失败标志
#define OTP_PROGEN_FAIL_MASK     (0x01<<OTP_PROGEN_FAIL_POS)

#define OTP_PROGEN_INIT_POS      3             //初始化状态
#define OTP_PROGEN_INIT_MASK     (0x01<<OTP_PROGEN_INIT_POS)

#define OTP_PROGEN_LOCK_POS      4             //编程锁定寄存器
#define OTP_PROGEN_LOCK_MSK      (0xFF<<OTP_PROGEN_LOCK_POS)


#define OTP_RDEN_EN_POS          0             //读操作使能
#define OTP_RDEN_EN_MASK         (0x01<<OTP_RDEN_EN_POS)

#define OTP_RDEN_ST_POS          1             //读操作状态寄存器
#define OTP_RDEN_ST_MASK         (0x01<<OTP_RDEN_ST_POS)

#define OTP_PROG_UNLOCK_POS      0             //解锁寄存器
#define OTP_PROG_UNLOCK_MSK      (0xFFFFFFFF<<OTP_PROG_UNLOCK_POS)


typedef struct {
	union {
		__IO uint32_t RDR;    //接收数据寄存器
		
		__IO uint32_t SDR;    //发送数据寄存器
		
		__IO uint32_t DLL;    //波特率低八位配置寄存器
	};
	union {
		__IO uint32_t DHL;    //波特率高八位配置寄存器
		
		__IO uint32_t IE;     //中断使能寄存器   
	};
	
	__IO uint32_t RIID;       //中断ID寄存器  只读
	
	__IO uint32_t CTRL;       //控制寄存器
	
	__IO uint32_t MCR;        //LOOPBACK使能 
	
	__IO uint32_t LSR;       //状态寄存器
	
} UART_TypeDef;



#define UART_IE_RXIEN_POS        0      //接收数据有效中断使能
#define UART_IE_RXIEN_MSK        (0x01 << UART_IE_RXIEN_POS)

#define UART_IE_TXE_POS          1      //发送数据寄存器空中断使能
#define UART_IE_TXE_MSK          (0x01 << UART_IE_TXE_POS)


#define UART_CTRL_DATALEN_POS    0      //数据位宽  00 5bit   01  6bit  10  7bit  11 8bit
#define UART_CTRL_DATALEN_MSK    (0x03 << UART_CTRL_DATALEN_POS)

#define UART_CTRL_STOP2BIT_POS   2      //停止位   0  1stop    1   2stop
#define UART_CTRL_STOP2BIT_MSK   (0x01 << UART_CTRL_STOP2BIT_POS)

#define UART_CTRL_PARITY_POS	 3		//000 无校验    001 奇校验   011 偶校验   101 固定为1    111 固定为0
#define UART_CTRL_PARITY_MSK	 (0x07 << UART_CTRL_PARITY_POS)

#define UART_CTRL_BRKEN_POS		 6		//Break控制使能
#define UART_CTRL_BRKEN_MSK		 (0x01 << UART_CTRL_BRKEN_POS)

#define UART_CTRL_BAUDEN_POS	 7		//波特率设置开启位
#define UART_CTRL_BAUDEN_MSK	 (0x01 << UART_CTRL_BAUDEN_POS)

#define UART_MCR_LOOPBACKEN_POS	 4      //回环模式使能位
#define UART_MCR_LOOPBACKEN_MSK	 (0x01 << UART_MCR_LOOPBACKEN_POS)
 
#define UART_LSR_REC_POS        0       //数据接收状态
#define UART_LSR_REC_MSK        (0x01 << UART_LSR_REC_POS)

#define UART_LSR_OVF_POS        1       //数据溢出状态
#define UART_LSR_OVF_MSK        (0x01 << UART_LSR_OVF_POS)

#define UART_LSR_PARITY_POS     2       //奇偶校验状态
#define UART_LSR_PARITY_MSK     (0x01 << UART_LSR_PARITY_POS)

#define UART_LSR_STOP_POS       3       //STOP状态
#define UART_LSR_STOP_MSK       (0x01 << UART_LSR_STOP_POS)

#define UART_LSR_BREAK_POS      4       //BREAK状态
#define UART_LSR_BREAK_MSK      (0x01 << UART_LSR_BREAK_POS)

#define UART_LSR_THRE_POS       5       //发送数据寄存器空状态
#define UART_LSR_THRE_MSK       (0x01 << UART_LSR_THRE_POS)

#define UART_LSR_TEMT_POS       6       //无发送数据状态
#define UART_LSR_TEMT_MSK       (0x01 << UART_LSR_TEMT_POS)


typedef struct {
	__IO uint32_t CLKDIV;       //分频寄存器 
	
	__IO uint32_t CTRL;         //控制寄存器  
	
	__IO uint32_t TXR;          //发送寄存器
	
	__IO uint32_t RXR;          //接收寄存器
	
	__IO uint32_t CR;           //命令寄存器
	
	__IO uint32_t SR;           //状态寄存器
	
} IIC_TypeDef;

#define IIC_CTRL_EN_POS    0    //模块使能
#define IIC_CTRL_EN_MSK    (0x01 << IIC_CTRL_EN_POS)

#define IIC_CTRL_IE_POS    1    //中断使能
#define IIC_CTRL_IE_MSK    (0x01 << IIC_CTRL_IE_POS)


#define IIC_CR_IF_POS      0    //清中断
#define IIC_CR_IF_MSK      (0x01 << IIC_CR_IF_POS)

#define IIC_CR_ACK_POS     1    //接收模式下，向总线反馈ACK
#define IIC_CR_ACK_MSK     (0x01 << IIC_CR_ACK_POS)

#define IIC_CR_WR_POS      2    //向从机写数据
#define IIC_CR_WR_MSK      (0x01 << IIC_CR_WR_POS)

#define IIC_CR_RD_POS      3    //从从机读数据
#define IIC_CR_RD_MSK      (0x01 << IIC_CR_RD_POS)

#define IIC_CR_STOP_POS    4    //产生STOP信号
#define IIC_CR_STOP_MSK    (0x01 << IIC_CR_STOP_POS)

#define IIC_CR_START_POS   5    //产生START信号
#define IIC_CR_START_MSK   (0x01 << IIC_CR_START_POS)


#define IIC_SR_IF_POS      0    //清中断
#define IIC_SR_IF_MSK      (0x01 << IIC_SR_IF_POS)

#define IIC_SR_TIP_POS     1    //传输进行中
#define IIC_SR_TIP_MSK     (0x01 << IIC_SR_TIP_POS)

#define IIC_SR_ARB_POS     2    //仲裁丢失
#define IIC_SR_ARB_MSK     (0x01 << IIC_SR_ARB_POS)

#define IIC_SR_BUSY_POS    3    //总线忙
#define IIC_SR_BUSY_MSK    (0x01 << IIC_SR_BUSY_POS)

#define IIC_SR_RACK_POS    4    //接收到从机发送过来的ACK
#define IIC_SR_RACK_MSK    (0x01 << IIC_SR_RACK_POS)


typedef struct {
	__IO uint32_t LPOW_MD;      //低功耗模式选择
	
	__IO uint32_t LPMD_WKEN;    //低功耗唤醒源使能
	
	__IO uint32_t LPMD_WKST;    //低功耗唤醒源状态
	
	uint32_t RESERVED1[5];
	
	__IO uint32_t TRIM_POW;     //POWER TRIM 
	
	__IO uint32_t TRIM_RC;      //RCHF RCLF TRIM
	
	__IO uint32_t TRIM_LOCK;    //TRIM LOCK
	
	uint32_t RESERVED2[1];
	
	__IO uint32_t RCHFCR;					//RC High speed Control Register
	
} PMU_TypeDef;


#define PMU_LPOW_MD_STANDBY_POS         0     //STANDBY模式
#define PMU_LPOW_MD_STANDBY_MSK         (0x01 << PMU_LPOW_MD_STANDBY_POS)

#define PMU_LPOW_MD_SLEEP_POS           1     //SLEEP模式
#define PMU_LPOW_MD_SLEEP_MSK           (0x01 << PMU_LPOW_MD_SLEEP_POS)

#define PMU_LPOW_MD_DEEPSLEEP_POS       2     //DEEPSLEEP模式
#define PMU_LPOW_MD_DEEPSLEEP_MSK       (0x01 << PMU_LPOW_MD_DEEPSLEEP_POS)

#define PMU_LPOW_MD_STOP_POS            3     //STOP模式
#define PMU_LPOW_MD_STOP_MSK            (0x01 << PMU_LPOW_MD_STOP_POS)

#define PMU_LPMD_WKEN_RTC_ALARM_POS     0     //低功耗模式下  RTC闹钟唤醒使能
#define PMU_LPMD_WKEN_RTC_ALARM_MSK     (0x01 << PMU_LPMD_WKEN_RTC_ALARM_POS)

#define PMU_LPMD_WKEN_RTC_SEC_POS       1     //低功耗模式下  RTC秒信号唤醒使能
#define PMU_LPMD_WKEN_RTC_SEC_MSK       (0x01 << PMU_LPMD_WKEN_RTC_SEC_POS)

#define PMU_LPMD_WKEN_IO_POS            2     //低功耗模式下  IO信号唤醒使能
#define PMU_LPMD_WKEN_IO_MSK            (0x01 << PMU_LPMD_WKEN_IO_POS)


#define PMU_LPMD_WKST_RTC_ALARM_POS     0     //低功耗模式下  RTC闹钟唤醒标志
#define PMU_LPMD_WKST_RTC_ALARM_MSK     (0x01 << PMU_LPMD_WKST_RTC_ALARM_POS)

#define PMU_LPMD_WKST_RTC_SEC_POS       1     //低功耗模式下  RTC秒信号唤醒标志
#define PMU_LPMD_WKST_RTC_SEC_MSK       (0x01 << PMU_LPMD_WKST_RTC_SEC_POS)

#define PMU_LPMD_WKST_IO_POS            2     //低功耗模式下  IO信号唤醒标志
#define PMU_LPMD_WKST_IO_MSK            (0x01 << PMU_LPMD_WKST_IO_POS)


#define PMU_TRIM_LOCK_POS		        0	//TRIM_LOCK       写入0x55锁定TRIM寄存器
#define PMU_TRIM_LOCK_MSK		        (0xFF << PMU_TRIM_LOCK_POS)


#define PMU_RCHFCR_EN_POS		        0	//RCHF使能
#define PMU_RCHFCR_EN_MSK		        (0x01 << PMU_RCHFCR_EN_POS)


typedef struct {
	__IO uint32_t CFG;          //CACHE配置寄存器      
	
	__IO uint32_t PF_CTRL;      //预取控制寄存器   	
} CACHE_TypeDef;


#define CACHE_CFG_RESET_POS       0              //CACHE复位信号
#define CACHE_CFG_RESET_MSK       (0x01 << CACHE_CFG_RESET_POS)

#define CACHE_CFG_IDLE_POS        1              //CACHE空闲状态
#define CACHE_CFG_IDLE_MSK        (0x01 << CACHE_CFG_IDLE_POS)


#define CACHE_PF_CTRL_START_POS   0              //预取启动位
#define CACHE_PF_CTRL_START_MSK   (0x01 << CACHE_PF_CTRL_START_POS)

#define CACHE_PF_CTRL_UNLOCK_POS  1              //预取解锁配置寄存器
#define CACHE_PF_CTRL_UNLOCK_MSK  (0x01 << CACHE_PF_CTRL_UNLOCK_POS)

#define CACHE_PF_CTRL_ADDR_POS    4             //预取空间的基地址
#define CACHE_PF_CTRL_ADDR_MSK    (0x1FF << CACHE_PF_CTRL_ADDR_POS)


typedef struct {
	__IO uint32_t CFG;               //ADC配置寄存器      
	
	__IO uint32_t START;             //ADC启动寄存器  

	__IO uint32_t IE;                //ADC中断使能寄存器  
	
	__IO uint32_t IF;                //ADC中断状态寄存器  
	
 	struct {
		__IO uint32_t STAT;          //通道状态寄存器
		
		__IO uint32_t DATA;          //通道数据寄存器
		
	    uint32_t RESERVED1[2];
	} CH[9];
	
	__IO uint32_t FIFO_STAT;         //FIFO状态寄存器
	
	__IO uint32_t FIFO_DATA;         //FIFO数据寄存器
	
	uint32_t RESERVED2[14];
	
	__IO uint32_t CTRL;              //ADC控制寄存器 
	
	uint32_t RESERVED3[3];
	
	__IO uint32_t CALIB_OFFSET;     //ADC校准OFFSET寄存器
	
	__IO uint32_t CALIB_KD;         //ADC校准KD寄存器
	
} ADC_TypeDef;


#define ADC_CFG_CH0_Pos			    0		//通道0选中
#define ADC_CFG_CH0_Msk			    (0x01 << ADC_CFG_CH0_Pos)

#define ADC_CFG_CH1_Pos			    1		//通道1选中
#define ADC_CFG_CH1_Msk			    (0x01 << ADC_CFG_CH1_Pos)

#define ADC_CFG_CH2_Pos			    2		//通道2选中
#define ADC_CFG_CH2_Msk			    (0x01 << ADC_CFG_CH2_Pos)

#define ADC_CFG_CH3_Pos			    3		//通道3选中
#define ADC_CFG_CH3_Msk			    (0x01 << ADC_CFG_CH3_Pos)

#define ADC_CFG_CH4_Pos			    4		//通道4选中
#define ADC_CFG_CH4_Msk			    (0x01 << ADC_CFG_CH4_Pos)

#define ADC_CFG_CH5_Pos			    5		//通道5选中
#define ADC_CFG_CH5_Msk			    (0x01 << ADC_CFG_CH5_Pos)

#define ADC_CFG_CH6_Pos			    6		//通道6选中
#define ADC_CFG_CH6_Msk			    (0x01 << ADC_CFG_CH6_Pos)
 
#define ADC_CFG_CH7_Pos			    7		//通道7选中
#define ADC_CFG_CH7_Msk			    (0x01 << ADC_CFG_CH7_Pos)

#define ADC_CFG_CH8_Pos			    8		//通道8选中
#define ADC_CFG_CH8_Msk			    (0x01 << ADC_CFG_CH8_Pos)

#define ADC_CFG_AVG_Pos		        9		//0 1次采样	  1 2次采样取平均值	  2 4次采样取平均值	  3 8次采样取平均值	
#define ADC_CFG_AVG_Msk		        (0x03 << ADC_CFG_AVG_Pos)

#define ADC_CFG_CONT_Pos		    11		//Continuous conversion，只在软件启动模式下有效，0 单次转换，转换完成后START位自动清除停止转换
#define ADC_CFG_CONT_Msk		    (0x01 << ADC_CFG_CONT_Pos)							//   1 连续转换，启动后一直采样、转换，直到软件清除START位

#define ADC_CFG_SMPL_SETUP_Pos      12      //ADC外部采样时钟方式下采样建立时间   0:1  1:2  2:4  3:8  4:16  5:32  6:64  7:128
#define ADC_CFG_SMPL_SETUP_Msk      (0x07 << ADC_CFG_SPL_SETUP_Pos)

#define ADC_CFG_MEM_MODE_Pos        15      //ADC数据存储方式选择   0:FIFO模式   1:通道模式
#define ADC_CFG_MEM_MODE_Msk        (0x01 << ADC_CFG_MEM_MODE_Pos)

#define ADC_CFG_SMPL_CLK_Pos        16      //ADC采样模式选择    0:内部采样时钟  1:外部采样时钟
#define ADC_CFG_SMPL_CLK_Msk        (0x01 << ADC_CFG_SMPL_CLK_Pos)

#define ADC_CFG_IN_SMPL_WIN_Pos     17      //ADC内部采样时钟方式采样窗口设置   0:1Tclk   1:3Tclk   2:5Tclk   3:7Tclk  4:9Tclk  5:11Tclk  6:13Tclk  7:15Tclk
#define ADC_CFG_IN_SMPL_WIN_Msk     (0x07 << ADC_CFG_IN_SMPL_WIN_Pos)

#define ADC_CFG_EN_Pos              20      //ADC使能控制位   0:不使能  1:使能
#define ADC_CFG_EN_Msk              (0x01 << ADC_CFG_EN_Pos)

#define ADC_CFG_EN_AVDDSNS_Pos      21      //ADC VDD检测使能常开控制位   0:只有通道8有效时,VDD检测使能才打开   1:VDD检测使能常开
#define ADC_CFG_EN_AVDDSNS_Msk      (0x01 << ADC_CFG_EN_AVDDSNS_Pos)


#define ADC_START_START_Pos         0      //ADC启动信号   0:不启动  1:启动
#define ADC_START_START_Msk         (0x01 << ADC_START_START_Pos) 

#define ADC_START_BUSY_Pos          1      //ADC忙状态   0:空闲  1:忙
#define ADC_START_BUSY_Msk          (0x01 << ADC_START_BUSY_Pos) 

#define ADC_START_SOFT_RESET_Pos    2      //ADC软复位使能位
#define ADC_START_SOFT_RESET_Msk    (0x01 << ADC_START_SOFT_RESET_Pos) 

#define ADC_START_FIFOCLR_Pos       3      //ADC FIFO清除使能
#define ADC_START_FIFOCLR_Msk       (0x01 << ADC_START_FIFOCLR_Pos) 


#define ADC_IE_CH0EOC_Pos			0		//CH0转换完成中断使能
#define ADC_IE_CH0EOC_Msk			(0x01 << ADC_IE_CH0EOC_Pos)

#define ADC_IE_CH1EOC_Pos			1		//CH1转换完成中断使能
#define ADC_IE_CH1EOC_Msk			(0x01 << ADC_IE_CH1EOC_Pos)

#define ADC_IE_CH2EOC_Pos			2		//CH2转换完成中断使能
#define ADC_IE_CH2EOC_Msk			(0x01 << ADC_IE_CH2EOC_Pos)

#define ADC_IE_CH3EOC_Pos			3		//CH3转换完成中断使能
#define ADC_IE_CH3EOC_Msk			(0x01 << ADC_IE_CH3EOC_Pos)

#define ADC_IE_CH4EOC_Pos			4		//CH4转换完成中断使能
#define ADC_IE_CH4EOC_Msk			(0x01 << ADC_IE_CH4EOC_Pos)

#define ADC_IE_CH5EOC_Pos			5		//CH5转换完成中断使能
#define ADC_IE_CH5EOC_Msk			(0x01 << ADC_IE_CH5EOC_Pos)

#define ADC_IE_CH6EOC_Pos			6		//CH6转换完成中断使能
#define ADC_IE_CH6EOC_Msk			(0x01 << ADC_IE_CH6EOC_Pos)

#define ADC_IE_CH7EOC_Pos			7		//CH7转换完成中断使能
#define ADC_IE_CH7EOC_Msk			(0x01 << ADC_IE_CH7EOC_Pos)

#define ADC_IE_CH8EOC_Pos			8		//CH8转换完成中断使能
#define ADC_IE_CH8EOC_Msk			(0x01 << ADC_IE_CH8EOC_Pos)

#define ADC_IE_FIFO_FULL_Pos	    9       //FIFO满中断使能
#define ADC_IE_FIFO_FULL_Msk	    (0x01 << ADC_IE_FIFO_FULL_Pos)

#define ADC_IE_FIFO_HFULL_Pos	    10       //FIFO半满中断使能
#define ADC_IE_FIFO_HFULL_Msk	    (0x01 << ADC_IE_FIFO_HFULL_Pos)

#define ADC_IE_FIFO_OVF_Pos			11		//FIFO溢出中断使能
#define ADC_IE_FIFO_OVF_Msk			(0x01 << ADC_IE_FIFO_OVF_Pos)


#define ADC_IF_CH0EOC_Pos			0		//CH0转换完成中断状态
#define ADC_IF_CH0EOC_Msk			(0x01 << ADC_IF_CH0EOC_Pos)

#define ADC_IF_CH1EOC_Pos			1		//CH1转换完成中断状态
#define ADC_IF_CH1EOC_Msk			(0x01 << ADC_IF_CH1EOC_Pos)

#define ADC_IF_CH2EOC_Pos			2		//CH2转换完成中断状态
#define ADC_IF_CH2EOC_Msk			(0x01 << ADC_IF_CH2EOC_Pos)

#define ADC_IF_CH3EOC_Pos			3		//CH3转换完成中断状态
#define ADC_IF_CH3EOC_Msk			(0x01 << ADC_IF_CH3EOC_Pos)

#define ADC_IF_CH4EOC_Pos			4		//CH4转换完成中断状态
#define ADC_IF_CH4EOC_Msk			(0x01 << ADC_IF_CH4EOC_Pos)

#define ADC_IF_CH5EOC_Pos			5		//CH5转换完成中断状态
#define ADC_IF_CH5EOC_Msk			(0x01 << ADC_IF_CH5EOC_Pos)

#define ADC_IF_CH6EOC_Pos			6		//CH6转换完成中断状态
#define ADC_IF_CH6EOC_Msk			(0x01 << ADC_IF_CH6EOC_Pos)

#define ADC_IF_CH7EOC_Pos			7		//CH7转换完成中断状态
#define ADC_IF_CH7EOC_Msk			(0x01 << ADC_IF_CH7EOC_Pos)

#define ADC_IF_CH8EOC_Pos			8		//CH8转换完成中断状态
#define ADC_IF_CH8EOC_Msk			(0x01 << ADC_IF_CH8EOC_Pos)

#define ADC_IF_FIFO_FULL_Pos	    9       //FIFO满中断状态
#define ADC_IF_FIFO_FULL_Msk	    (0x01 << ADC_IF_FIFO_FULL_Pos)

#define ADC_IF_FIFO_HFULL_Pos	    10       //FIFO半满中断状态
#define ADC_IF_FIFO_HFULL_Msk	    (0x01 << ADC_IF_FIFO_HFULL_Pos)

#define ADC_IF_FIFO_OVF_Pos			11		//FIFO溢出中断状态
#define ADC_IF_FIFO_OVF_Msk			(0x01 << ADC_IF_FIFO_OVF_Pos)


#define ADC_STAT_EOC_Pos			0		//向ADC_IF相应通道对应位写1可清零
#define ADC_STAT_EOC_Msk			(0x01 << ADC_STAT_EOC_Pos)
#define ADC_STAT_OVF_Pos			1		//读数据寄存器清除
#define ADC_STAT_OVF_Msk			(0x01 << ADC_STAT_OVF_Pos)


#define ADC_DATA_DATA_Pos           0       //ADC通道数据寄存器
#define ADC_DATA_DATA_Msk           (0xFFF << ADC_DATA_DATA_Pos)

#define ADC_DATA_NUM_Pos            12      //ADC数据对应的通道编号
#define ADC_DATA_NUM_Msk            (0x0F << ADC_DATA_NUM_Pos)


#define ADC_FIFO_STAT_FULL_Pos      0       //ADC数据FIFO满标志位
#define ADC_FIFO_STAT_FULL_Msk      (0x01 << ADC_FIFO_STAT_FULL_Pos)

#define ADC_FIFO_STAT_HFULL_Pos     1       //ADC数据FIFO半满标志位
#define ADC_FIFO_STAT_HFULL_Msk     (0x01 << ADC_FIFO_STAT_HFULL_Pos)

#define ADC_FIFO_STAT_EMPTY_Pos     2       //ADC数据FIFO空标志位
#define ADC_FIFO_STAT_EMPTY_Msk     (0x01 << ADC_FIFO_STAT_EMPTY_Pos)

#define ADC_FIFO_STAT_OVF_Pos       3       //ADC数据FIFO溢出标志位
#define ADC_FIFO_STAT_OVF_Msk       (0x01 << ADC_FIFO_STAT_OVF_Pos)

#define ADC_FIFO_STAT_LEVEL_Pos     4       //ADC数据FIFO水线设置
#define ADC_FIFO_STAT_LEVEL_Msk     (0x0F << ADC_FIFO_STAT_LEVEL_Pos)


#define ADC_FIFO_DATA_Pos           0       //ADC数据FIFO寄存器
#define ADC_FIFO_DATA_Msk           (0xFFF << ADC_FIFO_DATA_Pos)

#define ADC_FIFO_NUM_Pos            12      //ADC数据FIFO对应的通道编号
#define ADC_FIFO_NUM_Msk            (0x0F << ADC_FIFO_NUM_Pos)


#define ADC_CTRL_VREF_Pos           0       //ADC内部VREF选择   0:内部  1:外部
#define ADC_CTRL_VREF_Msk           (0x01 << ADC_CTRL_VREF_Pos)


#define ADC_CALIB_OFFSET_Pos        0       //ADC数据校准OFFSET
#define ADC_CALIB_OFFSET_Msk        (0xFF << ADC_CALIB_OFFSET_Pos)

#define ADC_CALIB_OFFSET_VALID_Pos  16      //ADC数据校准OFFSET数据是否有效
#define ADC_CALIB_OFFSET_VALID_Msk  (0xFF << ADC_CALIB_OFFSET_VALID_Pos)


#define ADC_CALIB_KD_Pos            0       //ADC数据校准KD
#define ADC_CALIB_KD_Msk            (0x3FF << ADC_CALIB_KD_Pos)

#define ADC_CALIB_KD_VALID_Pos      16      //ADC数据校准KD数据是否有效
#define ADC_CALIB_KD_VALID_Msk      (0xFF << ADC_CALIB_KD_VALID_Pos)


/******************************************************************************/
/*						 Peripheral memory map							  */
/******************************************************************************/
#define RAM_BASE		    ((uint32_t)0x20000000)
#define AHB_BASE			((uint32_t)0x40000000)
#define APB1_BASE		 	((uint32_t)0x40040000)
#define APB2_BASE			((uint32_t)0x400A0000)
#define OTP_DATA            ((uint32_t)0x41000000)

/* AHB Peripheral memory map */
#define SYS_BASE			(AHB_BASE + 0x00000)
#define PMU_BASE			(AHB_BASE + 0x01000)
#define CACHE_BASE	        (AHB_BASE + 0x02000)


/* APB1 Peripheral memory map */

#define WDT_BASE		    (APB1_BASE + 0x1000)
#define TIMER_BASE		    (APB1_BASE + 0x1800)
#define RTC_BASE			(APB1_BASE + 0x2000)
#define SPI_BASE		    (APB1_BASE + 0x3000)
#define UART1_BASE		    (APB1_BASE + 0x4000)
#define UART2_BASE		    (APB1_BASE + 0x4800)
#define IIC_BASE		    (APB1_BASE + 0x5000)

/* APB2 Peripheral memory map */
#define PORT_BASE			(APB2_BASE + 0x0000)
#define GPIOA_BASE		    (APB2_BASE + 0x1000)
#define GPIOB_BASE		    (APB2_BASE + 0x1800)
#define OTP_BASE		    (APB2_BASE + 0x3000)
#define AES128_BASE		    (APB2_BASE + 0x3800)
#define UART0_BASE		    (APB2_BASE + 0x7000)
#define PWMG_BASE			(APB2_BASE + 0xA000)
#define PWM0_BASE			(APB2_BASE + 0xA100)
#define PWM1_BASE			(APB2_BASE + 0xA200)
#define PWM2_BASE			(APB2_BASE + 0xA300)
#define PWM3_BASE			(APB2_BASE + 0xA400)
#define PWM4_BASE			(APB2_BASE + 0xA500)
#define ADC_BASE			(APB2_BASE + 0xB000)

/******************************************************************************/
/*						 Peripheral declaration							 */
/******************************************************************************/
#define SYS					((SYS_TypeDef  *) SYS_BASE)

#define PMU 				((PMU_TypeDef  *) PMU_BASE)

#define CACHE				((CACHE_TypeDef*) CACHE_BASE)

#define WDT					((WDT_TypeDef  *) WDT_BASE)

#define TIMER				((TIMER_TypeDef *) TIMER_BASE)

#define RTC				    ((RTC_TypeDef *) RTC_BASE)

#define SPI				    ((SPI_TypeDef  *) SPI_BASE)

#define IIC                 ((IIC_TypeDef  *) IIC_BASE)

#define PORT				((PORT_TypeDef *) PORT_BASE)

#define GPIOA				((GPIO_TypeDef *) GPIOA_BASE)

#define GPIOB				((GPIO_TypeDef *) GPIOB_BASE)

#define OTP			        ((OTP_TypeDef  *) OTP_BASE)

#define AES128			    ((AES128_TypeDef  *) AES128_BASE)

#define UART0				((UART_TypeDef *) UART0_BASE)
#define UART1				((UART_TypeDef *) UART1_BASE)
#define UART2				((UART_TypeDef *) UART2_BASE)

#define PWMG				((PWMG_TypeDef *) PWMG_BASE)
#define PWM0				((PWM_TypeDef  *) PWM0_BASE)
#define PWM1				((PWM_TypeDef  *) PWM1_BASE)
#define PWM2				((PWM_TypeDef  *) PWM2_BASE)
#define PWM3				((PWM_TypeDef  *) PWM3_BASE)
#define PWM4				((PWM_TypeDef  *) PWM4_BASE)

#define ADC				    ((ADC_TypeDef  *) ADC_BASE)


#include "system_BL210x.h"
#include "BL210x_port.h"
#include "BL210x_gpio.h"
#include "BL2101_clk.h"
#include "BL2101_exti.h"
#include "BL2101_timer.h"
#include "BL2101_uart.h"
#include "BL2101_spi.h"
#include "BL2101_wdt.h"
#include "BL2101_rtc.h"
#include "BL2101_pwm.h"
#include "BL2101_otp.h"
#include "BL2101_aes.h"
#include "BL2101_iic.h"
#include "BL2101_power.h"
#include "BL2101_conf.h"
#include "BL2101_adc.h"



#endif //__BL2101_H__
